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Altera_Forum
Honored Contributor I
864 Views

DDR-SDRAM ALTERA FPGA interface problem.

Hi, 

I'm new here and a beginner for SOPC builder.I built my SOPC for DDR SDRAM interface.However it got some problem.I used Nios II Cyclone II dev.board. 

Everything is success during SOPC generation.I create PLL outside the SOPC, 150Mhz for DDR clk and 150Mhz(-90degeree) for DDR_write_clock. 

Error: Following DDIO Output nodes could not be placed by the Fitter 

Error: DDIO Node "nios_ddr:inst|ddr_sdram_component_classic_0: 

the_ddr_sdram_component_classic_0|ddr_sdram_component_classic_0_auk_ddr 

_sdram:ddr_sdram_component_classic_0_auk_ddr_sdram_inst|ddr_sdram_ 

component_classic_0_auk_ddr_datapath:ddr_io|ddr_sdram_component_ 

classic_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir: 

dqs_io|ddio_bidir_50l:auto_generated|output_cell_L[0]" could not be constrained to a legal location..........................:confused: 

 

Please help me.:)
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2 Replies
Altera_Forum
Honored Contributor I
46 Views

I face this problem before. You have to do some setting because there is too much bidir pins for 1 Vref.:) 

 

1st : 

Assigment-Device-Device and Pins option-Dual purpose pins(set all value to: use as regular I/O accept for DClock&nCEO. 

2nd : 

Assigment-Assigment Editor- Change all DQ,DQS and DM pins to (Output Enable Group). For the Value column, set any number same for those pins. 

eg: DQ[0]->Output Enable Group->123456(Value) 

3rd : 

Assigment-Pins(Change IO standard for all DDR related pins to SSTL-2 Class I.) 

 

You now are able to compile without any fail hopefully. I face this before and want to help you.:o 

 

Thank you: 

Shahril
Altera_Forum
Honored Contributor I
46 Views

I meet the same problem in this work,I do what you say.but,it doesn't work.what should I do.please happle me.

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