Hi everyone,I have an implemenation of the FFT megacore, currently under the Avalon ST interface In front of this I have a fifo the data coming in to the system is relatively slow, possibly irregular time periods Is it safe to use clock gating on the FFT/Avalon interface as a means to hold it back (even though this could be mid packet) while collecting more data ? Or is it better to de-assert the valid? or both? Hope you can point me the right way, Regards Pete B
--- Quote Start --- clock gating isn't really safe in FPGAs. It is better to use the valid signal and deassert it when you don't have any new data to give to the Avalon sink. --- Quote End --- Ok, thanks, so deasserting Valid mid packet doesnt do any harm though? Thanks again
no it shouldn't. The sink will just wait until there is valid data again.Be sure to check the ready signal too. A data sample is only transferred from a source to a sink when both the valid and ready signals are asserted.