DDR SDRAM High Performance Controller - are lots of warnings normal?

[Altera_Forum]

I have compiled the example design which is included within the DDR SDRAM High Performance Controller under Quartus II v9.0 for Cyclone III and I get lots of warnings (none critical). I am configuring the IP for a x16 device e.g. the Micron MT46V16M16TG-5B and accepting default settings - e.g. Avalon and AFI interfaces. 

 Some of these warning suggest there may be problems with the design. For example the first warning I get is:  Warning (10230): Verilog HDL assignment warning at ddr_auk_ddr_hp_controller_wrapper.v(166): truncated value with size 2 to match size of target (1)  This appears because the localparam gDWIDTH_RATIO is set to 4 when it would need to be 2 to get the sizes to match. There are lots more warnings like this. There are also warnings like:  Warning (10027): Verilog HDL or VHDL warning at the ddr_phy_alt_mem_phy_seq.vhd(8781): index expression is not wide enough to address all of the elements in the array  and  Warning (12110): Net "ddr_example_top:ddr_example_top_inst|ddr:ddr_inst|ddr_controller_phy:ddr_controller_phy_inst|ddr_phy:ddr_phy_inst|ddr_phy_alt_mem_phy:ddr_phy_alt_mem_phy_inst|resync_clk_1x[0]" is missing source, defaulting to GND  Are all these warnings to be expected? If so is this documented by Altera anywhere? Any advice would be much appreciated. :rolleyes:

[Altera_Forum]

Yeah this is normal unfortunately. It would be nice if Altera's IP generated no warnings but it does. They are obviously innocuous but annoying nonetheless. It's a combination of two things: 

 1 - Altera not producing the cleanest code. This is understandable. The IP cores are highly configurable and it's easy to see how you would not pay attention to certain cases in your code generator. Also, the warnings are typical of mistakes we all make when writing parameterizable code. (widths of registers and their assignment values for example or a signal that is used under one configuration but not another).  2 - Quartus gives an extemely large amount of information to the user. Some tools would never even report a warning like this. And indeed it's not an error. The way the code is written is perfectly legal. Quartus is choosing to inform you of the warning in the event you think it might be a coding error (like for example if I created a register but forgot to specify how wide it was). Again, not a syntax error but a coding error nonetheless.  My guideline is this: Assume the warnings from the core are harmless. Altera does of course have bugs in their IP but for the most part, don't expect the synthesis warnings to be related to any kind of bug. What you should look for are any warnings from the core that might indicate something you've done wrong in connecting it. For example, if large portions of the IP core are being synthesized away, you've probably connected something wrong. In the case of the DDR controller, this will typically result in an error because your design will have DQ pins with nothing connected to them.  Jake

[Altera_Forum]

Thanks for the swift response Jake. It's good to know it's not something I was getting wrong so as you suggest I will just ignore all the warnings. Thanks again.