FFT IP Core 8.1

[Altera_Forum]

Hi, 

I m using FFT IP core for the first time. i have spent several hours and experimented on different size andn types of FFT Functions using startix II. I still cant get EOP right while using waveform simulation. i.e. in case of 64 points, i have tried a gap of 62,63,64 cycles between sop and eop but still i m getting source error 3(When EOP is asserted before N valid samples are accepted). There should be a point (far far away from sop) where if i insert EOP, i should get error 2 ("Missing EOP" is asserted if the FFT accepts N valid samples of an FFT frame, but it is not completed with an EOP signal.) but this error never occours. I m using 40ns clock time period and i have tried EOP at the end simulation uptil 20 usec. Still error code 3.  FFT user guide suggests that sink ready should be asserted high (which is an output). if i assert this signal high, FFT sets it to low after first SOP and it never gets high again. I am attaching both input and output vwf files.  ANY HELP WILL BE HIGHLY APPRICIATED.  Regards  Omar

[Altera_Forum]

Hi, 

I also tried using another module to control my FFT, still the same prob. FFT never even starts the SOP for the output. I am really stuck. Plz help.  All the proj files are attached.

[Altera_Forum]

K guys 

Sort of figured it out. 1) FFT core in 8p1 doesnt work (for me atleast). the controller i wrote worked for 7.2 where as no output for 8.1. 2) still getting source_error but it is code 2 this time and also at the same time output of FFT is there. error occurs after end of packets but output is valid in the packets.  may be som1 will find the right way to handle fft on quartus 8.1

[Altera_Forum]

--- Quote Start ---  Hi, I m using FFT IP core for the first time. i have spent several hours and experimented on different size andn types of FFT Functions using startix II. I still cant get EOP right while using waveform simulation. i.e. in case of 64 points, i have tried a gap of 62,63,64 cycles between sop and eop but still i m getting source error 3(When EOP is asserted before N valid samples are accepted). There should be a point (far far away from sop) where if i insert EOP, i should get error 2 ("Missing EOP" is asserted if the FFT accepts N valid samples of an FFT frame, but it is not completed with an EOP signal.) but this error never occours. I m using 40ns clock time period and i have tried EOP at the end simulation uptil 20 usec. Still error code 3.  FFT user guide suggests that sink ready should be asserted high (which is an output). if i assert this signal high, FFT sets it to low after first SOP and it never gets high again. I am attaching both input and output vwf files.  ANY HELP WILL BE HIGHLY APPRICIATED.  Regards  Omar  --- Quote End ---    i have similar pro.:confused: Would someone help me?

[Altera_Forum]

This FFT is really unpredictable. The cntroller which works for me in uni, doesnt work when i use it at home. however i'll attach the controller which works with quartus 7.2 (most of the time though). genrate a symbol file for this controller and assert the sink ready and reset high in BDF file. Use the BDF file to provide inputs and monitor outputs. this is a 1024 point FFT controller with 16 bits. It instanciates the megacore genrated FFT named "FFT", so change the name if u use a diff name. 

 good luck  regards  Omar Anwar

[Altera_Forum]

Salaam Omar, 

 I'm also having some trouble with FFT v8.0, although in my case I think I am talking to the FFT block correctly, but I'm getting unexpected results. In my case I'm using a Nios processor, but you might be able to get the protocol information by looking at my code. Have a look at my post here (http://www.alteraforum.com/forum/showthread.php?t=4200). We might be able to help each other.  --Amr

[Altera_Forum]

Sorry AMR, 

i wish i could help you but i am not using NIOS. But my best guess would be that the ausio codec of yours is not working properly. thats y, u get nothing at PC.   Good luck   Omar

[Altera_Forum]

Hi, 

 I'm testing FFT mega core v8.1 with Quartus waveform simulator and i'm not getting any results in the output, which is always 0. Can anyone help me understand what is happening??  Thank you.   Duarte Carona

[Altera_Forum]

Go for altera 7.2 because 8.0 or 8.1 didnt work for me either. 

also try n write a controller (to provide all the control signals with accurate timing) to test the FFT Core and plot its output and input in waveform simulator. Waveform simulator inputs wont help u as accurate input timings are very hard to implement in waveform.   Best of Luck

[Altera_Forum]

How do you easily enter in meaningful input to the FFT for simulation?

[Altera_Forum]

Well, for simulation u will have to use garbage values. if u are getting output start of frame(s) and end of frame(s) at proper locations along with other valid signals, purpose of simulation is achieved. For testing on FPGA, you will have to use either a MIF or HEX file to initialize memory with proper data. Or u can use analog audio input (if it is on ur board) to provide data at run time but this is bit tricky coz of audio codec issues. 

 Good Luck

[Altera_Forum]

I saw your code Omar. I would like to ask only about how you gave the inputs to sink_real. 

 Thanks Mohammed

[Altera_Forum]

sink_ready can not be forced to be high. It is an output from the fft generated file

[Altera_Forum]

Hello everyone, 

 I have a problem with the FFT 8.1, too. I created an instance with the Megawizard. I chose a burst architecture with a single output, 1024 points, 16bit data width and 16bit twiddle width. I simulated and it works fine. BUT the goal is to connect the FFT instance to the Nios II.    Therefore I wrote a wrapper that matches the Avalon Streaming interface. I merged the 16bit imaginary and real signals to one 32bit bus at the input and the output. The exponent output, which is intended to be read after processing a block of e.g. 1024 points, can be read via an additional Avalon interface I added. So far so good.   I connected the FFT input and output to a FIFO each with a size of 1024 times 32bit. Between the FFT and the FIFOs I placed a timing adapter each, which adapts the read latency from 1 cycle (FIFO) to 0 (FFT).    FIFO --> Timing Adapter --> FFT (Wrapper)--> Timing Adapter --> FIFO   To prevent the FFT reading data from the FIFO everytime a 32bit value is written to it, the sink_ready signal of the FFT is ANDed with a signal, that is writeable by the processor.  The FIFO shall be written until it is full. Then the FFT sink_ready shall be released and the FFT shall read the 1024x32bit values in a burst until EOP is applied by the FIFO.    Problem: If I write data to the FIFO, it outputs a SOP signal after the first data, because the Timing Adapter includes a small FIFO and is ready to receive data. This SOP is hold at the output of the timing adapter, also if the FFT does not apply a sink_ready. This makes the FFTinstance blocking, after it outputs several SOP's, until it is reset entirely. STRANGE!!!   The behavior can be seen in screenshot attached.   Has somebody an Idee how to solve this problem? Or has somebody a better solution to connect the FFT to the Nios II? Using SGDMAs is not a preferred solution, except somebody has a working solution. ...I tried this for weeks. :-(

[Altera_Forum]

I think that you can do the FFT Core and get the result easily using verilog. Then you can create a user component in the SOPC builder and passing the 32 bits to it which in turn will pass these 32 bits to the NIOS. 

I hope this is useful.

[Altera_Forum]

I got the FFT 8.1 working with the Nios II!!!! 

 First of all, the OPTIONAL signal clockenable is not optional. If you do not add it via the Wizard and apply a fixed value of 1(high) to it, the generated IP-core will not behave like in the simulation. In my case the IP-core only accepted 7 times 32bit and than de-asserted the ready signal until it was reset.    I used a 1024points FFT with 16bit data width, Burst Architecture, a Single Output and "Add ClockEnable" checked. I wrote a wrapper around the created IP-core including two FIFOs and some status and control registers. The two 16bit inputs and outputs are merged. The 6bit Exponent Output which is required for scaling the results is readable via an additional Avalon-MM-slave Port.    I spend more than 14 days on this problem, because of the documantation of Altera...

[Altera_Forum]

I would like to ask you that why you need to do all that? You can only pass the source_real and source_imag to the NIOS. 

 In your simulation, can you take the NIOS code into your account?? or you only simulate the verilog code. I think you are using the waveform file for simulation purposes.