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Altera_Forum
Honored Contributor I
934 Views

DDR SDRAM controller Compilations error in Cyclone III

Hi 

 

I am trying to build a project with a Nios II/f processor and a DDR SDRAM interface on a Cyclone III FPGA. 

 

I have used the preset for the Micron MT46V14M16TG. The controller can only run at 100 MHz or faster due to a bug in the mega wizard, but my Nios II processor cannot run that fast. (I would have expected it to in a Cyclone III!!!). Therefor I have modified the DQ width so my DDR controller runs twice as fast as my local bus and I keep a local data width of 32 bits.  

 

I use TimeQuest and the SDC file generated by the DDR mega wizard 

 

I keep getting an compilations error when i run the fitter in Quartus II with a design with a DDR SDRAM controller and I cannot figure out how to fix it :(  

 

This is the error I get: 

 

Critical Warning: Could not find pin of type addrcmd_2t from pattern *ddr_phy_alt_mem_phy_ciii_inst|adc|odt[*].odt_struct|half_rate.addr_pin|auto_generated|ddio_outa[0]|dataout 

Warning: Ignored assignment create_clock 

Warning: "5,882" is not a valid time value 

Warning: Invalid assignment for clock: ddr_phy_ddr_capture The option -period has the following error: Invalid clock period. Clock was not created or updated. 

Warning: Ignored assignment set_false_path 

Warning: Argument -from with value [get_clocks {ddr_phy_ddr_capture}] contains zero elements 

Error: Too Few items in collection (0) for list c 

while executing 

"error "Too Few items in collection ($i) for list $vlist"" 

(procedure "sett_collection" line 14) 

invoked from within 

"sett_collection c [get_pins -compatibility_mode $measure_pattern]" 

(file "C:/altera/designs/ddr_sdram/ddr_phy_ddr_timing.sdc" line 389) 

Critical Warning: Read_sdc failed due to errors in the SDC file 

Error: Can't fit design in device 

Error: Quartus II Fitter was unsuccessful. 2 errors, 17 warnings 

Info: Allocated 204 megabytes of memory during processing 

Error: Processing ended: Thu Sep 06 22:46:32 2007 

Error: Elapsed time: 00:00:10 

Error: Quartus II Full Compilation was unsuccessful. 2 errors, 17 warnings 

 

It seems like if the compiler cannot read the SDC file  

 

Have anybody seen this before or have a suggestion of what the problem is? 

 

Best Regards 

 

Tom
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3 Replies
Altera_Forum
Honored Contributor I
47 Views

Hi 

 

I have tried to change some , to a . in the SDC file which seems to fix the "invalid number" errors. I have also tried to comment out the line which causes the previous error, but then I get this error: 

 

Critical Warning: Could not find pin of type addrcmd_2t from pattern *ddr_phy_alt_mem_phy_ciii_inst|adc|odt[*].odt_struct|half_rate.addr_pin|auto_generated|ddio_outa[0]|dataout 

Error: can't use non-numeric string as operand of "+" 

while executing 

"expr {$board_skew + $tDS + $WR_DQS_DQ_SETUP_ERROR}" 

("foreach" body line 13) 

invoked from within 

"foreach dqsgroup $pins(dqsgroup) { 

set dqspin [lindex $dqsgroup 0] 

# DQS output clock 

set dqs_out_clockname "${corename}_ddr_dqsout_${dqspin}" 

..." 

(file "C:/altera/designs/ddr_sdram/ddr_phy_ddr_timing.sdc" line 408) 

Critical Warning: Read_sdc failed due to errors in the SDC file 

 

I am not familiar with the syntax in the SDC file so I have not been able to debug it. 

 

Have anybody seen this error before or have a suggestion. 

 

I do not get what I am doing wrong. I cannot find the problem in the Errata Sheet for the DDR & DDR2 SDRAM High-Performance Controller so I must be doing something wrong. 

 

Best Regards 

 

Tom
Altera_Forum
Honored Contributor I
47 Views

I have fixed the last error by changing , to . in all numbers in the file (I wonder why the file is generated with , in the numbers ????), but I still get the first error. If I comment out the line then I can compile the design, but the deign does not work in the FPGA. 

 

The line I comment out is: 

 

sett_collection c [get_pins -compatibility_mode $measure_pattern] 

 

Does anybody know what the problem is in this line and do I need it or can I comment it out? 

 

I do not know if I should file an error report to Altera or if it is my own fault that I get all these problems. 

 

Regards 

 

Tom
Altera_Forum
Honored Contributor I
47 Views

Altera support have helped me find the last error. I had not noticed that the sdram_clk and the sdram_clk_n are both bidirectional. When this error is fixed the design compiles. I have not tested the design on my board yet, but hopefully everything works.... 

Altera also informed me that the error in the SDC file where numbers are written with commas instead of dots will be fixed in Quartus 7.2. Until then you will have to fix it manually yourself in the SDC file. 

 

Regards 

 

Tom
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