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Altera_Forum
Honored Contributor I
749 Views

2S60 Demo Design that Came with DSP Builder

This definitely caused me (and my Altera FAE) alot of sleepless nights. I thought I would share what I learned with everyone here. 

 

With version 7.0, it seems like there are some mistakes with the 2S60 demo design that came with DSP Builder. 

 

If I just run the design as it is then ADC1 output is pure noise. 

 

Mainly, this was due to the fact that the 2S60 board block from DSP Builder library had the wrong clock assignments. If you double click on the 2S60 block, the following parameters are set: 

 

 

--- Quote Start ---  

 

  • Clock Pin In: Pin_AM17 

  • Clock Pin Out (D2A_2_CLK): Pin_C16 

  • Clock Pin Out (D2A_1_CLK): Pin_B15 

  • Clock Pin Out: Pin_B18 

  • Clock Pin Out: Pin_C15 

  • Clock Pin Out (inverted): Pin_D16 

  • Clock Pin Out (inverted): Pin_D18 

  • Global Reset Pin: Pin_AG19 

 

 

--- Quote End ---  

 

 

However, in the board schematics, those pins actually refer to the following: 

 

 

--- Quote Start ---  

 

  • AM17 -> PLD_CLKIN0 

  • C16 -> DAC_PLLCLK2 

  • B15 -> DAC_PLLCLK1 

  • B18 -> ADC_PLLCLK1 

  • C15 -> DAC_PLLCLK1_N 

  • D16 -> DAC_PLLCLK2_N 

  • D18 -> ADC_PLLCLK2 

  • AG19 -> PLD_CLEAR_N 

 

 

--- Quote End ---  

 

 

It almost seems like some of the default clock settings were wrong. If everything were labeled properly, only four clocks would be needed, one to drive each output (2 ADCs and 2 DACs). Therefore, I changed it to the following: 

 

 

--- Quote Start ---  

 

  • Clock Pin In: Pin_AM17 

  • Clock Pin Out (D2A_2_CLK): Pin_C16 

  • Clock Pin Out (D2A_1_CLK): Pin_B15 

  • Clock Pin Out: Pin_D18 

  • Clock Pin Out: Pin_B18 

  • Clock Pin Out (inverted): None 

  • Clock Pin Out (inverted): None 

  • Global Reset Pin: Pin_AG19 

 

 

--- Quote End ---  

 

 

Another problem with the design is that in 7.0, the default DSP Builder DAC blocks do not have the proper pin assignments. An Altera AE got me the patch (which I have included below). To install the patch: 

 

 

--- Quote Start ---  

 

  • Close MATLAB/Simulink 

  • Place the attached files in the <Default DSP Builder root>/altlib (go ahead and replace the old files. 

  • Restart MATLAB/Simulink 

  • Replace the old DAC/ADC blocks with new ones from the DSP Builder library list. 

 

 

--- Quote End ---  

 

 

With the above two fixes, you should be able to get all four sine waves from all four channels (2 ADC and 2 DAC). However, the sine waves from the two ADC channel are a bit noisy (somewhat periodic noise). To get around that, I did the following: 

 

 

--- Quote Start ---  

 

  • Open up the automatically generated Quartus project. 

  • Expand the project architecture and double click on the PLL block to bring up the PLL megawizard GUI. 

  • Add an 180 degrees phase-shift to the output clock. 

  • Regenerate the PLL and recompile the Quartus project. 

  • Reprogram the board and re-run Signal Tap II. 

 

 

--- Quote End ---  

 

 

Voila! You should see clean sine waves from all four channels.
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2 Replies
Altera_Forum
Honored Contributor I
42 Views

Hi wronghorizon, 

 

Thanks for the much needed patches. 

 

I'm not very sure how to perform the last step of adding a 180 degrees phase-shift to the output clock. In my generated Quartus project, I've just have three VHDL files, two for dspbuilder and one for the actual VHDL file. I cannot find the PLL block. 

 

I'm also trying to assign pin for my separate Quartus block diagram so that I can have an equivalent Verilog file to compare against my dspbuilder project. Unfortunately in Quartus 7.0 there is NO pin_u14 for DAC A and pin_u15 for DAC B. I've checked with Quartus 6.0 but the pins are there. So I've changed the pins assignment to pin _B15 and pin_C16 in Quartus for DAC A and DAC B, respectively, as recommended in your dspbuilder example. Am I doing it correctly or do I need a separate patch for that. 

 

Regards, 

wimax
Altera_Forum
Honored Contributor I
42 Views

Hi Wimax, 

 

Sorry for the late reply. For the last step, the steps are outlined below: 

1. Start Analysis/Elaboration  

2. Then in the entity window, expand the design  

3. Once the design is expanded, you will see two instances of PLL 

4. Double click the PLL instances to bring up the megawizard... make sure clock phase shift is set to 180 degrees (under output clocks). (I believe the PLL that you have to change is the first one: dspboard2S60_pll:uclklk_out2p). 

5. Then recompille your design and it should work. 

 

FYI... I think this issue has been fixed in 7.1, therefore it should not be a problem anymore...
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