FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5985 Discussions

DDR and DDR2 SDRAM High-Performance Controller User Guide: question

Altera_Forum
Honored Contributor II
789 Views

Could somebody please explain the following from page 4-16 of 

the DDR and DDR2 SDRAM High-Performance Controller User Guide: 

 

To map local_wdata and local_be to mem_dq and mem_dm, consider the 

following full rate example with 32-bit wide local_wdata and 16-bit wide 

mem_dq. 

 

local_wdata = <22334455> <667788AA> <BBCCDDEE> 

local_be = <1100> <0110> <1010> 

These map to: 

mem_dq = <4455> <2233> <88AA> <6677> <DDEE> <BBCC> 

mem_dm = <1 1> <0 0> <0 1> <1 0> <0 1> <0 1> 

 

how did they arrive at local_be and mem_dm? 

Thanks MikeZ
0 Kudos
0 Replies
Reply