Hello people,I quite new to FPGA design and not to mention Qsys! I am trying to make a collection of 32 x 16bit registers used in a Qsys system to store data coming from a parallel port. My focus right now it to design a custom Qsys slave component that conforms to the Avalon MM interface. These registers will map to 32 16bit memory addresses (so 64Bytes of mapped memory). My main question is which Avalon MM signals are obligatory for this application? At first read I thought that I should need: - Clock - Reset - readdata (0..15) - writedata (0..15) - byteenable (0..1) (i do not need to assess each byte separately, so do I need this?) - read - write - chipselect (0..5) (Here is my basic question!) The chipselect question is: How does the Avalon MM system defines which component to choose based on the address? Is it done automatically? I followed the university program tutorial ''Making Qsys components'' where the Altera Monitor program was used to alter the memory directly. There the chipselect signal was used inside the component code to determine if the device was selected. When I removed the chipselect from the checks I got strange results. Why did this happen? When someone changes memory values in the Altera Monitor program what happens exactly? Is there a debug device inside the chip that acts as Master and writes the data I enter into the addresses that I choose from the Altera Monitor program? Thanks a lot in advance
You don't need any chipselect signal, because the read or write signals will only be asserted when your component is selected. You will need a 5-bit address vector though, to select which one of your 32 registers you want to read-write.The byteenable signals are optional, but if you don't use them you will have some strange behaviour with 16-bit access. One piece of advice, instead of using 16-bit data vectors, use 32-bit, even if you only actually use the low 16 bits. Then your component would use 128 bytes of mapped memory, with only the low 2 MSB of each 4-byte word actually active. The problem if you stick to 16-bit data vectors is that even if you want the CPU to do a 16-bit access, it will in fact do a 32-bit access, that will be translated to two 16-bit accesses by the fabric. For example if you do a 16-bit write, your component will see two 16-bit writes at two different addresses, one with byteenable = "11" and one with byteenable="00". It can be a bit confusing and makes the component a bit more complex. So if the extra used memory space isn't a problem, it's better to make your component 32 bit. I don't know the Altera Monitor program, but my guess is that it's using the Nios CPU's JTAG debug module to control the bus, through it's data master.
Thanks for the answer!Maybe thats why i was seeing strange results on the Altera Monitor. The example i was using was with one 16 register and when I was modifying the memory of the register i was seeing the data being copied to the other 16 bits too. Maybe that had to do with 32bit accessing. Anyway my application will be as follows: I need to have 16 (data bidirectional pins) + 5 (address bidirectional pins) + 1 (interrupt output pin) + 1 (transfer clock input pin) = 23 pinouts out of the FPGA and I want to make a state-machine master component that will manage the tranfers in and out of the FPGA and a memory like block (shall i use on chip memory or make my own registers?). EDIT: I will not be using the NIOS II processor! The state machine component will be as follows: Using the interrupt pin (INT goes LOW) the state machine will initiate read transaction from an external (out of the FPGA) chip and the chip will use its clock (rising and falling edges) to transmit parallel data to the FPGA by placing the address it wants into the address pins and the 16bit data it wants to the datapins. Analogously when the state machine makes the INT go HIGH then a write transaction is initiated and the external chip puts the address on the address pins and the state machine puts the data on the data pins. Again the write transactions are synchronized with the external chip clock (which is much slower than the FPGA clock) To sum up this state machine has to write to the 32x16bit register (or memory) when it reads data from the external chip and and read data from the other 32x16bit register (or memory) when it writes data to the external chip. An issue is that the FPGA data pins are bidirectional (how do i accomplish tht with VHDL) The system is illustrated below https://www.alteraforum.com/forum/attachment.php?attachmentid=7254
It shouldn't be a lot of trouble to implement. Just remember that all inputs to your state machine must be properly synchronized. I particular all the signals coming from outside the FPGA will need to be fed to several registers in series. If you don't see what I'm talking about, google "clock domain crossing".As for the bidirectional pins, they need to be defined as "inout" ports in the VHDL code, and then you can read or write them. To use a pin as an output just write a '0' or a '1' to it, and to use it as an input, write 'Z' to it (high impedance) and read its value.
Thanks a lot!Basically the external clock is not really a clock it is something like a slow interrupt signal where in its rising and falling edge a transfer will be made. So i just need to check with my much faster FPGA clock whether this clock signal went HIGH or LOW and initiate a read or write transfer with the external chip. Since my state machine master component will be rising edge and reset synchronized why should I use a register for this input?
Also I forgot to say (after seeing a clock domain crossing article) that i do not have access to the external chip clock so i cannot latch this clock-interrupt signal. The name clock confuses a little bit but as i said it is not the external device's clock but just a signal that triggers (with its rising and falling edge) read and write transfers.Also another question! Since I am not using the Nios II, can I use multiple masters acting upon the custom register components?