recently, i am working on can bus communication of fpga. i downlownded an ip core from opencore. i use the ip core through c8051 interface. it is bulit in the system like:https://www.alteraforum.com/forum/attachment.php?attachmentid=7256 , i process the ip core in nios like this: void Write_Reg(alt_u8 addr, alt_u8 reg_data)
{
//write reg
ALE_LOW;
SJA_CS_HI;
RD_HI;
WR_HI;
ALE_HI;
PORT_OUT;
usleep(1);
IOWR_ALTERA_AVALON_PIO_DATA(CAN_DAT_BASE,addr);//写地址
usleep(1);
ALE_LOW;
SJA_CS_LOW;
WR_LOW;
usleep(1);
//PORT_IN;
IOWR_ALTERA_AVALON_PIO_DATA(CAN_DAT_BASE,reg_data);//写数据
WR_HI;
SJA_CS_HI;
ALE_HI;
}
alt_u8 Read_Reg(alt_u8 addr)
{ alt_u8 reg_data;
WR_HI;
SJA_CS_HI;
ALE_HI;
//read reg
ALE_LOW;
RD_HI;
WR_HI;
SJA_CS_HI;
ALE_HI;
usleep(1);
PORT_OUT;
IOWR_ALTERA_AVALON_PIO_DATA(CAN_DAT_BASE,0);//写地址
usleep(1);
ALE_LOW;
SJA_CS_LOW;
RD_LOW;
usleep(1);
PORT_IN;
reg_data=IORD_ALTERA_AVALON_PIO_DATA(CAN_DAT_BASE);//读数据
usleep(1);
RD_HI;
SJA_CS_HI;
return reg_data;
} simulate as its reading and writing timing.
https://www.alteraforum.com/forum/attachment.php?attachmentid=7257 https://www.alteraforum.com/forum/attachment.php?attachmentid=7258 but it's always 0xff when i read from the SJA1000 regs no matter what value i write to its regs.
