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PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

DDR on CIII

Altera_Forum
Honored Contributor II
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Hi all, 

 

I have question regarding DDR memory controller. 

 

Is it possible to implement DDR protocol for NAND FLASH memory controller without using dedicated FPGA's DQ/DQS pair? if yes then how? 

 

thanks, 

 

regards, 

Vijay
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