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DDR2 Controller Lock Up Mid Read Operation

Altera_Forum
Honored Contributor II
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We are implementing a DDR2 interface using the avalon MM master templates provided by Altera. The issue is that on occasion, we will assert a read request to the avalon read master and the read process never finishes. Using SignalTap to debug it was determined that the read master has begun to read data out from the DDR2 but does not finish. The issue is that the "waitrequest" signal goes high during the read, and is never deasserted, causing a lockup. I would like any insight for this issue you can give me. We have been trying to debug this for a long time and the deadline to get this working is very soon. The interface width is 32 bits on each side, it is made sure that all write and read lengths/addresses are on a 4 byte boundary. It is made sure that the length and address signals are held stable multiple cycles before the "go" signal is asserted. It is made sure that the FIFO is empty at the beginning of a read. It is made sure the address is not exceeding the memory limit or bit width. The board is a custom board, with routing rules being adhered to for the ddr2 lines (impedance controlled/length matched). Is there any idea what might be causing this? What seems to significantly reduce the probability of this happening is to disable "force burst alignment". Enabling/disabling burst seems to also alter this probability, but nothing we have tried so far completely alleviates the situation. Does anyone have any insights? I can provide my source code and setup in a limited fashion if necessary.

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