DDR2 HP Controller Random Writes

[Altera_Forum]

Hi, 

I am running a new design with MT47H64M16HR from micron. The chip is CY3 55 -6. Half rate local native mode. Currently at 150MHz, but we have verified the design using nios with 200MHz memclock.(Still half rate).  The reads are perfoming well, burst reads are performed con't. But the writes are a different story. As far as I know the controller should accept 4 commands in a burst. If within same column it should burst. But I get 12 clock latency for every write, no matter the address.  The CL is set to 4.  Any ideas?  Is it possible to use the old legacy controller on Cy3? Much less hassle.  apus

[Altera_Forum]

Is it, Altera SDRAM controller or HPDDR2? I implemented HPDDR2 for 4 consecutive writes and 2 reads...it works well with CL 5

[Altera_Forum]

Hi, 

at CL5 the controller never assert ready. It is the HP DDR2. What speed did you use? The same SDRAM?  apus