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5950 Discussions

DDR2 HP simulation fail in StratixIV

Altera_Forum
Honored Contributor II
913 Views

hi all, 

I want to simulate DDR2 HP ip core. I use the altera example as top file. 

According to altera docment, I do the following: 

1. I download simulation model from Micron and add `define sg37E 

`define x8 and `include "ddr2_parameters.vh" to simulation model 

2. create DDR2 HP core and generate simulation model 

3. modify tb file. replace altera mem_model with Micron model 

4. compile the library 

vlib altera_library# basic libraries 

vlib altera_library/lpm 

vmap lpm altera_library/lpm 

vcom -93 -work lpm {d:/tools/quartus9.1/quartus/eda/sim_lib/220pack.vhd} 

vcom -93 -work lpm {d:/tools/quartus9.1/quartus/eda/sim_lib/220model.vhd} 

vlib altera_library/altera 

vmap altera altera_library/altera 

vcom -93 -work altera {d:/tools/quartus9.1/quartus/eda/sim_lib/altera_primitives_components.vhd} 

vcom -93 -work altera {d:/tools/quartus9.1/quartus/eda/sim_lib/altera_primitives.vhd} 

vcom -93 -work altera {d:/tools/quartus9.1/quartus/eda/sim_lib/altera_syn_attributes.vhd} 

vcom -93 -work altera {d:/tools/quartus9.1/quartus/libraries/vhdl/altera/altera_europa_support_lib.vhd} 

vlib altera_library/altera_mf 

vmap altera_mf altera_library/altera_mf 

vcom -93 -work altera_mf {d:/tools/quartus9.1/quartus/eda/sim_lib/altera_mf_components.vhd} 

vcom -93 -work altera_mf {d:/tools/quartus9.1/quartus/eda/sim_lib/altera_mf.vhd} 

vlib altera_library/sgate 

vmap sgate altera_library/sgate 

vcom -93 -work sgate {d:/tools/quartus9.1/quartus/eda/sim_lib/sgate_pack.vhd} 

vcom -93 -work sgate {d:/tools/quartus9.1/quartus/eda/sim_lib/sgate.vhd}# component dependent libraries# ALTGXB 

vlib altera_library/ALTGXB 

vmap ALTGXB altera_library/ALTGXB 

vcom -93 -work ALTGXB {d:/tools/quartus9.1/quartus/eda/sim_lib/stratixiv_hssi_components.vhd} 

vcom -93 -work ALTGXB {d:/tools/quartus9.1/quartus/eda/sim_lib/stratixiv_hssi_atoms.vhd}# stratixiv 

vlib altera_library/stratixiv 

vmap stratixiv altera_library/stratixiv 

vcom -93 -work stratixiv {d:/tools/quartus9.1/quartus/eda/sim_lib/stratixiv_atoms.vhd} 

vcom -93 -work stratixiv {d:/tools/quartus9.1/quartus/eda/sim_lib/stratixiv_components.vhd}# stratixiii 

vlib altera_library/stratixiii 

vmap stratixiii altera_library/stratixiii 

vcom -93 -work stratixiii {d:/tools/quartus9.1/quartus/eda/sim_lib/stratixiii_atoms.vhd} 

vcom -93 -work stratixiii {d:/tools/quartus9.1/quartus/eda/sim_lib/stratixiii_components.vhd}# stratixgx 

vlib altera_library/stratixgx 

vmap stratixgx altera_library/stratixgx 

vcom -93 -work stratixgx {d:/tools/quartus9.1/quartus/eda/sim_lib/stratixgx_mf.vhd} 

vcom -93 -work stratixgx {d:/tools/quartus9.1/quartus/eda/sim_lib/stratixgx_mf_components.vhd} 

5. compile the HDL file, the step is ok. 

vlib work 

vmap work work 

vcom -93 -work work {d:/ddr-s/sim/ddr2_phy_alt_mem_phy_pll.vhd} 

vcom -93 -work work {d:/ddr-s/sim/ddr2_phy_alt_mem_phy_seq_wrapper.vho} 

vcom -93 -work work {d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho} 

vcom -93 -work work {d:/ddr-s/sim/ddr2_phy.vho} 

vcom -93 -work work {d:/ddr-s/sim/ddr2.vhd} 

vlog -work work {d:/ddr-s/sim/ddr2_micron.v} 

vcom -93 -work work {d:/ddr-s/sim/ddr2_example_top.vhd} 

vcom -93 -work work {d:/ddr-s/sim/ddr2_controller_phy.vhd} 

vcom -93 -work work {d:/ddr-s/sim/ddr2_phy_alt_mem_phy_pll.vhd} 

vcom -93 -work work {d:/ddr-s/sim/ddr2_phy_alt_mem_phy_seq.vhd} 

vcom -93 -work work {d:/ddr-s/sim/ddr2_example_driver.vhd} 

vcom -93 -work work {d:/ddr-s/sim/ddr2_ex_lfsr8.vhd} 

vcom -93 -work work {d:/ddr-s/sim/ddr2_example_top_tb.vhd} 

6. then I do simulation, but I fail. I don't know the reason. 

vsim -t ps -novopt work.ddr2_example_top_tb 

 

Please help me check if I miss any HDL file。 

I attached the error information in the attachment file. 

 

thank you very much. 

Tom
0 Kudos
4 Replies
Altera_Forum
Honored Contributor II
154 Views

hi all, 

the error picture size is too big, so I copy it here.# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_controller_phy.vhd(384): No default binding for component at 'ddr2_auk_ddr_hp_controller_wrapper_inst'.# (Port 'cs_n' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_controller_phy.vhd(384): No default binding for component at 'ddr2_auk_ddr_hp_controller_wrapper_inst'.# (Port 'cke' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_controller_phy.vhd(384): No default binding for component at 'ddr2_auk_ddr_hp_controller_wrapper_inst'.# (Port 'ck_n' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_controller_phy.vhd(384): No default binding for component at 'ddr2_auk_ddr_hp_controller_wrapper_inst'.# (Port 'ck' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'odt' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'dqs_n' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'dqs' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'dq' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'addr' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'ba' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'dm_rdqs' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'we_n' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'cas_n' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'ras_n' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'cs_n' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'cke' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'ck_n' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'ck' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Warning: (vsim-3473) Component instance "ddr2_phy_ddr2_phy_alt_mem_phy_ddr2_phy_alt_mem_phy_inst_ddr2_phy_alt_mem_phy_dp_io_dpio_ddr2_phy_alt_mem_phy_delay_delay_gen_0_postamble_preset_delay_8840 : ddr2_phy_alt_mem_phy_delay" is not bound.# Time: 0 ps Iteration: 0 Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_phy_inst File: d:/ddr-s/sim/ddr2_phy.vho# ** Warning: (vsim-3473) Component instance "ddr2_phy_ddr2_phy_alt_mem_phy_ddr2_phy_alt_mem_phy_inst_ddr2_phy_alt_mem_phy_dp_io_dpio_ddr2_phy_alt_mem_phy_delay_delay_gen_1_postamble_preset_delay_8839 : ddr2_phy_alt_mem_phy_delay" is not bound.# Time: 0 ps Iteration: 0 Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_phy_inst File: d:/ddr-s/sim/ddr2_phy.vho# ** Warning: (vsim-3473) Component instance "ddr2_phy_ddr2_phy_alt_mem_phy_ddr2_phy_alt_mem_phy_inst_ddr2_phy_alt_mem_phy_dp_io_dpio_ddr2_phy_alt_mem_phy_dqs_ip_dqs_group_0_dqs_ip_ddr2_phy_alt_mem_phy_delay_dqs_enable_delay_8013 : ddr2_phy_alt_mem_phy_delay" is not bound.# Time: 0 ps Iteration: 0 Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_phy_inst File: d:/ddr-s/sim/ddr2_phy.vho# ** Warning: (vsim-3473) Component instance "ddr2_phy_ddr2_phy_alt_mem_phy_ddr2_phy_alt_mem_phy_inst_ddr2_phy_alt_mem_phy_dp_io_dpio_ddr2_phy_alt_mem_phy_dqs_ip_dqs_group_1_dqs_ip_ddr2_phy_alt_mem_phy_delay_dqs_enable_delay_7047 : ddr2_phy_alt_mem_phy_delay" is not bound.# Time: 0 ps Iteration: 0 Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_phy_inst File: d:/ddr-s/sim/ddr2_phy.vho# Error loading design# Error: Error loading design # Pausing macro execution # MACRO ./compile.do PAUSED at line 19 

 

regards 

tom
Altera_Forum
Honored Contributor II
154 Views

why no people answer my question? 

 

Regards 

tom
Altera_Forum
Honored Contributor II
154 Views

Hallo Tom, 

 

I would like to ask you if you could solve this problem? 

If yes, How did you do it? 

 

I am having a similar situation when I use the DDR2 HPC II with my own testbench. Apparently, it is because the Modelsim-ALTERA edition that I am using does not support the mixed HDL. 

 

However, when I am simulating the DDR2 HPC II with the example generated by the megawizard I do not have any problems. 

 

Therefore I am very curious what could it be this kind of error. I suppose it is a problem loading the libraries. :S 

 

Thanks, 

Juan
Altera_Forum
Honored Contributor II
154 Views

I think I found a possible solution for your error: 

 

Go to settings menu -> Simulation -> TestBenches ->  

 

Then in for your testbench add the .vho files together with the testbench file and the memory model file.  

Then there must be no error. 

 

Regards, 

Juan
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