DDR2 High Performance Con V7.1 SDC file difference between Stratix III and Stratix II

[Altera_Forum]

Hi 

 I create a DDR2 High Performance Controller V7.1 with a stratix II device and find that the auto-generated SDC file include many constraints, such as DQ/DQS/Addr/Cmd output delay, DQ input delay, clock max delay, false path,etc. But When I create the same controller with a stratix III device, the auto-generated SDC file doesn't include DQ/DQS output delay, DQ input delay, clock max delay. It only includes Addr/Cmd output delay and less false paths. I have two questions: 1. Why there are so many differences between stratix II and stratix III?  2. Should I add the DQ/DQS output delay and DQ input delay and the others into SDC file when I use TimeQuest to analyze timing with DDR2 High Performance Controller in stratix III?  If someone knows about it, please tell me.  Thanks

[Altera_Forum]

Hello, 

Sorry, I can give you my advice, because I use Stratix II only.  But I think you are profession in my issues, I need your help. I have some troubles with my design. I use MegaWizard in Quartus's Web edition(not create High performance Controller), to create ALTMEMPHY. It releases many files such as: *_alt_mem_phy_reconfig_sii *_alt_mem_phy_ sii alt_mem_phy_defines alt_mem_phy_sequencer.vhd *_altmem_phy_sequencer_wrapper.vo ... Module "alt_mem_phy_sequencer.vhd" is encrypted, so I can't see anything. How can I use this module? To ensure my logic is ok, I simulate them with my logic by using NCverilog 5.5. But the way ALTMEMPHY tool uses parameter is new to me. And when I run my simulation, it can not stop and print out may warnings. So you can give me your advice. I'm very impressed by ALTMEMPHY but I can't use it for a long time. Thank you in advance!

[Altera_Forum]

--- Quote Start ---  Hi  I create a DDR2 High Performance Controller V7.1 with a stratix II device and find that the auto-generated SDC file include many constraints, such as DQ/DQS/Addr/Cmd output delay, DQ input delay, clock max delay, false path,etc. But When I create the same controller with a stratix III device, the auto-generated SDC file doesn't include DQ/DQS output delay, DQ input delay, clock max delay. It only includes Addr/Cmd output delay and less false paths. I have two questions: 1. Why there are so many differences between stratix II and stratix III?  2. Should I add the DQ/DQS output delay and DQ input delay and the others into SDC file when I use TimeQuest to analyze timing with DDR2 High Performance Controller in stratix III?  If someone knows about it, please tell me.  Thanks  --- Quote End ---   HI shsong ,  can you provide your ddr2 controller sdc file for reference?  regards --sampath