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Dear All,
I am finding below compilation error in DDR2 memory controller. I am using stratix III device. Error: Illegal connection found on I/O input buffer primitive DDR_2_top:dut|DDR_2:R_2_inst|DDR_2_controller_phy:R_2_controller_phy_inst|DDR_2_phy:R_2_phy_inst|DDR_2_phy_alt_mem_phy:R_2_phy_alt_mem_phy_inst|DDR_2_phy_alt_mem_phy_clk_reset:clk|gen_mimic_diff_ibuf.fb_clk_ibuf. Source IO FATEC_DDR_2_top:dut|DDR_2:R_2_inst|DDR_2_controller_phy:R_2_controller_phy_inst|DDR_2_phy:R_2_phy_inst|DDR_2_phy_alt_mem_phy:R_2_phy_alt_mem_phy_inst|DDR_2_phy_alt_mem_phy_clk_reset:clk|DDR_CLK_OUT[0].mem_clk_obuf~0 also drives out to other destination than the buffer. Any idea about the error? Best Regards, CheevuLink Copied
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As per data sheet mem_clk and mem_clk_n need to be connected as bi directional port even though for DDR2 interface is an input
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cool~~~~~~
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readed.......
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