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DDR2 SDRAM Controller with ALTMEMPHY - CIVGX

Altera_Forum
Honored Contributor I
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Hello, 

Is possible to interface a DDR2-800 [1] to the Cyclone IV GX -C7? 

 

According the EMI Spec Estimator [2], the memory interface of the FPGA Cyclone IV GX Speed Grade -7 supports up to 167 MHz when is allocated on the top side banks and the controller runs in half rate mode. The estimator indicates that the speed grade of the memory device must be at least 200 MHz. With this configuration, is possible to interface a DDR2-800 (400MHz)?  

 

The interface pins are ok and the memory preset file was prepared correctly. However, analyzing in SignalTap the FPGA does not pass the initialization stage (local_init_done is always '0', cal_fail is '1' and cal_success is '0'). 

 

Based on the reference design for Cyclone IV GX Dev Kit which uses a DDR2-533 (266 MHz)[3], the IP was configurated with Memory Clock Frequency : 167 MHz and Controller data rate in Half mode. In that case the DDR2-533 runs at slower frequency than its maximum, then the DDR2-800 could runs at slower frequency than its maximum too? 

 

Thank you, I will appreciate your help. 

 

 

[1] http://www.alliancememory.com/pdf/ddr2/1gb-as4c64m16d2.pdf 

[2] http://wl.altera.com/technology/memory/estimator/supportselector.html# 

[3] http://icdemi.com/manual/mt47h64m4,mt47h32m8,mt47h16m16.pdf
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