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FPGA Intellectual Property

Discussions

Mobile DDR read and write fails on some addresses

Microtronix Mobile DDR sdram controller

trouble making a custom vip usign data_valid signal

dummy core between two VIP using SOPC builder

component editor

Implement FFT in parallel

Refresh w/ DDR2 HPC 10.1

Problem in altfp_sincos megafunction.

how can i get a free avalon based i2c slave

DMA & FIR Filter, some questions.

Reset signal for blocks in DSPBuilder model

Need video and image processing megacores

Difference between board reset and power-on reset

CAN bus controller with avalon interface

compilation problem in simulation

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Tone Mapping Operator IP Malfunctioning

dynamic configuration issue of fpll from arria 10

Unable to simulate DDR3 controller

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)