Hello,I have a question about the implementation of FFT in parallel. In the system, I have one main clock, let's call it Fsys. I have several data streams, with a lower rate than Fsys. So the idea is to use a clock with a lower frequency for the FFT also (else I would need to put a memory before the FFTs). The data streams are all at the same rate but the packets are shifted by one Fsys cycle, as shown in the joined picture. To respect the diagram presented in the FFT user Guide (i.e data changing only on rising edge of FFT clock), I should provide to each FFT its own control signals (clock, start of packet, end of packet, cf top of joined picture). The problem with this is that the number of FFTs to implement would be about 30/40. So I don't think it is possible to generate such number of clock with PLLs, and I will have problem with timing if I generate one clock with a PLL and then use flip-flops for the others. Another idea is to share the control signals between all the FFT as shown at the bottom of the joined picture. For me, this should work fine since all the signals are synchronized with Fsys and I should not have problem of timing. But I would like to have the opinion of others about this way to do, if is good or not, since I don't respect anymore the diagram in the FFT user guide. The joined picture shows an example with the two methods, for a 4 points-FFT with a data rate 4 times lower than the main clock. If there are some elements not clear, tell, I will explain better/differently. Thanks in advance. Jérôme
--- Quote Start --- The problem with this is that the number of FFTs to implement would be about 30/40. Another idea is to share the control signals between all the FFT as shown at the bottom of the joined picture. For me, this should work fine ... --- Quote End --- Hi Jérôme. What are the sizes of the FFT's and the data rates you are working with? 30 to 40 FFT's seems unrealistic in a system. So you will probably have to buffer and reuse some of the fft's at least. As for the data alignment, Yes it should work, but you can remove the uncertainty by just simply adding a few delay line registers so that all the data and SOP/EOP signals are aligned going into the FFT's. Pete
Hi Pete,Thank you for your answer. In fact I have another way to deal with it. The main clock is about 200 MHz, the data rates can be between 150 kHz and 2 MHz appproximately. The size of the FFT can be between 64 and 512 points. But I use a large FPGA, so I can put a lot of FFTs inside. But now my idea is to multiplex the data stream, write them into a buffer, then read them (the addresses are not accessed in the same order for the writing and the reading, which implies in fact to have two buffers working in ping-pong) and process them with only one FFT ! Like this it is much simpler and much more efficient. Jérôme
Hi All,Does anyone know how to perform FFT using some FFT size and combine after completed all the chunk of data rather than using on big FFT size inside FPGA? For example, compute 32k FFT using 8192 FFT size with repeating 4x using the same 8k FFT? The reason to do this is to reutilized the FFT logic inside the FPGa in order to save logic consumption.