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Altera_Forum
Honored Contributor I
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Refresh w/ DDR2 HPC 10.1

I'm using a DDR2 HPC 10.1 in a Stratix IV and allowing the controller to handle the refresh. In testing the FPGA, I'm getting intermittent errors in the read data coming from the controller when there's a local_refresh_acq within about 30 clock cycles of the read request. I can't say for sure that the refresh is causing the problem. Would I be better off implementing a user-controlled refresh in my design to make sure the refresh is not a problem? 

 

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