DDR2 SDRAM controller & Avalon Burst

[asp_sem]

Good day!
The question is in the attachment.
Thank you in advance.

[sstrell]

What do you mean by a "shift" when reading the data in your question?  It's not clear what the issue is.

#iwork4intel

[asp_sem]

Hello. By shift in this case, I mean that the first value 1 is written at the initial address 25'd800000, and value 2 is read at the same address. And for some reason, the value 1 is read at the final address 25'd1454076.

Signal mem_rd_readdatavalid - this is a signal readdatavalid , and signal mem_rd_readdata - this is a signal readdata of avalon specification (burst transfer).

[sstrell]

So you're talking about the 1 at the very end of when readdatavalid is active?

What is the burstcount set to?  You may be reading from an address that you did not intend.

Check the Avalon spec for details on what a read burst looks like and verify.  See figure 15 here:

https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/mnl_avalon_spec.pdf

#iwork4intel

[asp_sem]

Yes, I'm talking about 1 at the very end when readdatavalid is active. But, each time reflashing the FPGA, this shift is different. In the end, there may be 1 and 2.

BurstCount = 4.

I am trying to find a discrepancy between my signal generation code and the avalon specification. But so far no result.