DDR2 SDRAM: local_init_done not going high

[Altera_Forum]

I have built a DDR2 SDRAM v7.2 controlller, v7.2, using the Megawizard and a native interface. I have reviewed my schematic and pinout and it looks to be correct. The local_init_done is not going high. I verified this using Signal Tap. Could I have a bad 2GB SODIMM module? Any ideas or thoughts would be great! 

 Thanks!

[Altera_Forum]

If the initial timing calibration fails, init_done won't be asserted. I would rather expect a wiring error than a bad RAM module.

[Altera_Forum]

Thanks for the reply... 

 Is there any way to prove it is a timing failure causing this? Is there another signal inside of the megawizard ddr2 function that I could look at?

[Altera_Forum]

I remember that I had a similar issue with a SODIMM DDR2 design, I even used ModelSim to understand the initialisation steps and observable signals. But it turned out as very basic wiring fault that would have been detected by checking the design more thoroughly. Usual timing problems are rather causing data errors than calibration failure. 

 As you probably know, DDIO pins are accessible with SignalTap, so you can't easily debug DDR RAM operation.

[Altera_Forum]

DDIO pins? Should I only be using certain pins? Do I need to instantiate DDIO between the DDR2 signals and the output pins...Sorry for the question...I'm really confused now. I know from memory(i'm at home and don't have access to my schematic) that I am using the pins on the bottom of the chip(AB-AJ), and I think mos of them are 1-20 as well. Thanks for help...I will look into this more tomorrow at work.

[Altera_Forum]

Suitable pins are selected during DDR2 Megacore implementation, either automaticly or with user interaction. Without correct pin assignment, the design wouldn't compile at all, you don't need to check it. I only wanted to mention the fact, that you can't use SignalTap with some RAM pins.

[Altera_Forum]

Thanks FvM. 

 My SODIMM has 64 bits. What mode should I use, x8/x9, x16,x18, x32,x36, x4, or x4 Mode? I have a Stratix II 1020 -3 FPGA. I'm looking at the Pin Information for Stratix II EP2s60 devide and it is confusing because it has DG group for DQs mode and the DQ group for non-DQS mode. I'll assume that since my Micron SODIMM module uses the DQS pins (non-differential), that I need to use the DQ group for DQS mode pins.   Thanks for all of your continued support.

[Altera_Forum]

For an SODIMM with 64 bits, ie. non-ecc, use x8/x9. If you right click on the picture of your part in pin planner, it will show a context menu. Click 'show DQ/DQS pins -> x8/x9'. The banks will appear to be color coded. 

 Each bank will have 8 DQ pins, 1 DM pin, and 1 DQS pin. If you are using differential DQS, then the bank will also have a DQS# pin. The DQS must go on the S pin and the DM and DQs all go on Q pins.  For more info, look at Altera AN 408.