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DDR2 SDRAM with UniPHY not generating half_rate_clock

Honored Contributor II

Hi there, 

I'm using Quartus 12.1 SP1 and generated a DDR2 SDRAM Controller with UniPHY via the MegaWizard Plugin Manager. 

The Memory Frequency is 400 MHz, PLL reference clock 50 MHz and the Rate on the Avalon-MM interface is set to Half. So I should have a 200MHz clock on the afi_clk pin. 

After I compiled the core once, I wanted to use the Half Rate Clock for another entity, controlling the USB Chip on my DE4 Board. So I checked the Box at "Enable AFI half rate clock". 

After conecting this clock pin to my Entity I got errors like 



--- Quote Start ---  

Warning (14130): Reduced register "ISP1761Control:ISP1761Control_INST|ISP1761HAL:isp_hal|state.READING1" with stuck clock port to stuck value GND 

Warning (14110): No clock transition on "ISP1761Control:ISP1761Control_INST|ISP1761HAL:isp_hal|state.WRITING1" register due to stuck clock or clock enable 


--- Quote End ---  


indicating there is no Clock on afi_half_clock. In the RTL Viewer afi_half_clock is driven by GND. 

I already deleted my db and incremental db folders and did a Analysis/Synthesis, but that did'nt change anything. Also running the pin_assignments script again didn't change anything. 


Am I missing something, or does this feature simply not work. 


Thanks in advance 


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3 Replies
Honored Contributor II

FWIW, I can confirm the above; these are my observations (Quartus 12.1 sp1, 12.1 uniphy, ddr2, stratix III) 

o the afi clock is active, hopefully it runs at half rate if its a half rate uniphy and at full rate if its a full rate uniphy consistent with the Uniphy functional description doc 

o the afi half clock always runs at 0 Hz, independent of whether its enabled or not in the megawizard gui
Honored Contributor II

FWIW, I think I see that this happens because of generated code as follows; seems to be independent of half-rate / full-rate controller setting. 


In <instance>/synthesis/submodules/<instance>_mem_if_ddr2_emif_pll0.sv we have some assignments. 


assign afi_clk = pll_afi_clk; 


assign afi_half_clk = 1'b0; 


This is service request 10945983.
Honored Contributor II

You can refer to the workaround for this issue: 


Problems with simulation of DDR2 SDRAM Controller with UniPHY