Problems with simulation of DDR2 SDRAM Controller with UniPHY

Altera_Forum · ‎11-04-2012

Hi,

I Am using the files for simulation in generated for this IP .

The IP is configured to enable Hard external memory controller, in Aria V, Quartus 12.

The DDR2 SDRAM Controller is set to work with A micron DDR2 : MT47H64M16HW_3IT.

I Have tried to simulate the IP and used the msim_setup.tcl script for that.

The compilation was fine but in simulation , the Micorn DDR2 model does not pass the initialization phase stating :

ERROR: Power Down Failure. Initialization sequence is not complete.

I have also noticed that the AFI_HALF_CLK drives '0' instead of driving half of the ddr2 clock.

The example design works but I can't use it as a functional simulation model in my design cause the interfaces do not match. I will appreciate your guidance with this issue.

Regards,

Daniel G.

Altera_Forum · ‎12-04-2012

I have also noticed the problems with afi_half_clk when upgrading to Quartus 12.1 When digging into the generated code for the pll the second to last line is "assign afi_half_clk = 1'b0;" I am pretty sure that is the source of the problem there. For the time being i an creating an external Pll to divide down the clock.

-Brian

Altera_Forum · ‎07-10-2013

> "assign afi_half_clk = 1'b0;"

I provide my workaround for above issue as follows:

S/W: Quartus II 12.0, SP2

Modified file: /[FPGA_PROJECT]/[QSYS_NAME]/synthesis/submodules/[QSYS_NAME]_uniphy_ddr3_pll0.sv

1. find the following codes:

altpll upll_memphy (

.areset (areset),

.inclk (inclk),

.clk (pll_clks),

.locked (pll_locked),

.activeclock (),

.clkbad (),

.clkena ({6{1'b1}}),

.clkloss (),

.clkswitch (1'b0),

.enable0 (),

.enable1 (),

.extclk (),

.extclkena ({PLL_PHASE_COUNTER_WIDTH{1'b1}}),

.fbin (1'b1),

.fbmimicbidir (),

.fbout (),

.fref (),

.icdrclk (),

.pfdena (1'b1),

.pllena (1'b1),

.scanaclr (1'b0),

.scanread (1'b0),

.scanwrite (1'b0),

.configupdate(1'b0),

.scandata(1'b0),

.scandataout(),

.scandone(),

.phasecounterselect({PLL_PHASE_COUNTER_WIDTH{1'b1}}),

.phasedone(),

.phasestep(1'b1),

.phaseupdown(1'b1),

.scanclk(1'b0),

.scanclkena(1'b1),

.sclkout0 (),

.sclkout1 (),

.vcooverrange (),

.vcounderrange ()

);

defparam upll_memphy.bandwidth_type = "AUTO";

defparam upll_memphy.clk0_divide_by = PLL_AFI_CLK_DIV;

defparam upll_memphy.clk0_duty_cycle = 50;

defparam upll_memphy.clk0_multiply_by = PLL_AFI_CLK_MULT;

defparam upll_memphy.clk0_phase_shift = PLL_AFI_CLK_PHASE_PS;

defparam upll_memphy.clk1_divide_by = PLL_MEM_CLK_DIV;

defparam upll_memphy.clk1_duty_cycle = 50;

defparam upll_memphy.clk1_multiply_by = PLL_MEM_CLK_MULT;

defparam upll_memphy.clk1_phase_shift = PLL_MEM_CLK_PHASE_PS;

defparam upll_memphy.clk2_divide_by = PLL_WRITE_CLK_DIV;

defparam upll_memphy.clk2_duty_cycle = 50;

defparam upll_memphy.clk2_multiply_by = PLL_WRITE_CLK_MULT;

defparam upll_memphy.clk2_phase_shift = PLL_WRITE_CLK_PHASE_PS;

defparam upll_memphy.clk3_divide_by = PLL_ADDR_CMD_CLK_DIV;

defparam upll_memphy.clk3_duty_cycle = 50;

defparam upll_memphy.clk3_multiply_by = PLL_ADDR_CMD_CLK_MULT;

defparam upll_memphy.clk3_phase_shift = PLL_ADDR_CMD_CLK_PHASE_PS;

defparam upll_memphy.clk5_divide_by = PLL_NIOS_CLK_DIV;

defparam upll_memphy.clk5_duty_cycle = 50;

defparam upll_memphy.clk5_multiply_by = PLL_NIOS_CLK_MULT;

defparam upll_memphy.clk5_phase_shift = PLL_NIOS_CLK_PHASE_PS;

defparam upll_memphy.clk6_divide_by = PLL_CONFIG_CLK_DIV;

defparam upll_memphy.clk6_duty_cycle = 50;

defparam upll_memphy.clk6_multiply_by = PLL_CONFIG_CLK_MULT;

defparam upll_memphy.clk6_phase_shift = PLL_CONFIG_CLK_PHASE_PS;

defparam upll_memphy.inclk0_input_frequency = REF_CLK_PERIOD_PS;

defparam upll_memphy.intended_device_family = DEVICE_FAMILY;

defparam upll_memphy.lpm_type = "altpll";

defparam upll_memphy.operation_mode = "NO_COMPENSATION";

defparam upll_memphy.pll_type = "AUTO";

defparam upll_memphy.port_activeclock = "PORT_UNUSED";

defparam upll_memphy.port_areset = "PORT_USED";

defparam upll_memphy.port_clkbad0 = "PORT_UNUSED";

defparam upll_memphy.port_clkbad1 = "PORT_UNUSED";

defparam upll_memphy.port_clkloss = "PORT_UNUSED";

defparam upll_memphy.port_clkswitch = "PORT_UNUSED";

defparam upll_memphy.port_fbin = "PORT_UNUSED";

defparam upll_memphy.port_fbout = "PORT_UNUSED";

defparam upll_memphy.port_inclk0 = "PORT_USED";

defparam upll_memphy.port_inclk1 = "PORT_UNUSED";

defparam upll_memphy.port_locked = "PORT_USED";

defparam upll_memphy.port_pfdena = "PORT_UNUSED";

defparam upll_memphy.port_pllena = "PORT_UNUSED";

defparam upll_memphy.port_configupdate = "PORT_UNUSED";

defparam upll_memphy.port_scandata = "PORT_UNUSED";

defparam upll_memphy.port_scandataout = "PORT_UNUSED";

defparam upll_memphy.port_scandone = "PORT_UNUSED";

defparam upll_memphy.port_phasecounterselect = "PORT_UNUSED";

defparam upll_memphy.port_phasedone = "PORT_UNUSED";

defparam upll_memphy.port_phasestep = "PORT_UNUSED";

defparam upll_memphy.port_phaseupdown = "PORT_UNUSED";

defparam upll_memphy.port_scanclk = "PORT_UNUSED";

defparam upll_memphy.port_scanclkena = "PORT_UNUSED";

defparam upll_memphy.port_scanaclr = "PORT_UNUSED";

defparam upll_memphy.port_scanread = "PORT_UNUSED";

defparam upll_memphy.port_scanwrite = "PORT_UNUSED";

defparam upll_memphy.port_clk0 = "PORT_USED";

defparam upll_memphy.port_clk1 = "PORT_USED";

defparam upll_memphy.port_clk2 = "PORT_USED";

defparam upll_memphy.port_clk3 = "PORT_USED";

defparam upll_memphy.port_clk4 = "PORT_USED";

defparam upll_memphy.port_clk5 = "PORT_USED";

defparam upll_memphy.port_clk6 = "PORT_USED";

defparam upll_memphy.port_clk7 = "port_unused";

defparam upll_memphy.port_clk8 = "PORT_UNUSED";

defparam upll_memphy.port_clk9 = "PORT_UNUSED";

defparam upll_memphy.port_clkena0 = "PORT_UNUSED";

defparam upll_memphy.port_clkena1 = "PORT_UNUSED";

defparam upll_memphy.port_clkena2 = "PORT_UNUSED";

defparam upll_memphy.port_clkena3 = "PORT_UNUSED";

defparam upll_memphy.port_clkena4 = "PORT_UNUSED";

defparam upll_memphy.port_clkena5 = "PORT_UNUSED";

defparam upll_memphy.self_reset_on_loss_lock = "OFF";

defparam upll_memphy.using_fbmimicbidir_port = "OFF";

defparam upll_memphy.width_clock = 10;

2. modify: defparam upll_memphy.port_clk7 = "PORT_UNUSED";

to: defparam upll_memphy.port_clk7 = "port_used";

3. add following codes after instanced altpll upll_memphy():

defparam upll_memphy.clk7_duty_cycle = 50;

defparam upll_memphy.clk7_multiply_by = pll_afi_half_clk_mult;

defparam upll_memphy.clk7_phase_shift = pll_afi_half_clk_phase_ps;

defparam upll_memphy.clk7_divide_by = pll_afi_half_clk_div;

4. find: assign afi_half_clk = 1'b0;

modify it to: assign afi_half_clk = pll_clks[7];

note: Each time you re-generate Qsys system, you should do above workaround again...

Hope this is usefule.:)