DDR2 clock from PLL out

[nome]

hello

I am using Arria ii gx FPGA in Nios processor.altmemphy IP and our board main clock is 50 mhz
i want to know about interfacing between DDR2 clock to FPGA
my customize board connected the DDR2 clock with the differential pair pin AJ16 and AJ15.
My question is about the PLL dedicated pin how to create or assign dedicated pin in my top level design
Thanks
Nome

[EBERLAZARE_I_Intel]

Hi,

In Quartus, you can open the Assignments > Pin Planner.

For pin out you may find your board:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/lit-dp.html#tab-blade-1-2

[EBERLAZARE_I_Intel]

Hi,

Was my previous answer helpful to you? Do you have any further questions?

[nome]

Hello.

Thanks for your reply.

Not helpful .....!

My simple question is: which PLL out for DDR2 differential clock do I have to use? In our case, the Arria II GX is using pin AJ16 and AJ15 for the

DDR2 clock and assigning PLL C0 and FPGA main clock is 50mhz and PLL C0 100mhz DDR IP Refclk.

during compilation critical warnings occurring 

Warning(15899): PLL"nios_cpu:inst0_nios_cpu|lms_ctr:lms_ctr_inst0|lms_ctr_ddr2_1:ddr2_1|lms_ctr_ddr2_1_controller_phy:lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy:lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy:lms_ctr_ddr2_1_phy_alt_mem_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_clk_reset:clk|lms_ctr_ddr2_1_phy_alt_mem_phy_pll:half_rate.pll|altpll:altpll_component|altpll_mto3:auto_generated|pll1" has parameters clk2_multiply_by and clk2_divide_by specified but port CLK[2] is not connected

how possible assign? In SDC file

please help us

Thanks

[EBERLAZARE_I_Intel]

Hi,

First thing you need to check your board schematics on the available pins and the exact clock pins of your device, what is your part number of your device?

You need to verify the functionally of the pins in the pin out:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/lit-dp.html#tab-blade-1-2

Once that done, open Quartus, you can open the Assignments > Pin Planner, and select the specific "CLK" pins that was reported you have in your top level, and assign it accordingly in the "Location" tab in Pin Planner.

Once done, you can close the Pin Planner and double check in your Assignment Editor, if done correctly you should see a green "tick" on the specific "CLK" pins that you have assigned.

[EBERLAZARE_I_Intel]

Hi,

Do you have further questions?

[nome]

Hello

How to remove this warnings !

Warning (15899): PLL "nios_cpu:inst0_nios_cpu|lms_ctr:lms_ctr_inst0|lms_ctr_pll_0:pll_0|lms_ctr_pll_0_altpll_sgc2:sd1|pll7" has parameters clk2_multiply_by and clk2_divide_by specified but port CLK[2] is not connected

Thanks 

Nome

[EBERLAZARE_I_Intel]

Hi,

You need to locate the CLK[2] in your Pin Planner in Quartus, then assign that pin to location based on your schematics' Clock Pin.

[nome]

Hello,

Thanks for your reply.

The main 50MHz clock for the Arria II GX FPGA is fed from pin F17. The pin specification in the Pin Planner designates it as a dedicated clock, CLK 14, and Diffclk_4n.

My question is, how do I assign CLK[14] instead of CLK[2]?

please find attachment 

Thanks

Nome

[EBERLAZARE_I_Intel]

Hi,

The pin assignment can be made in Pin Planner, can you screenshot your pin planner.?

[nome]

Hi

Thanks for your Reply

Please find attachment

Thanks

Nome

[EBERLAZARE_I_Intel]

Hi,

From your Quartus error and the "node name" in Pin Planner it is seem to be mismatch, please check the exact clock name in your that is defined in your top_level.v or top_level.qsys. That clock name should be the clock pin that you assign the PIN_F17. in Pin Planner.

FYI, I will be out until Christmas, and I will get back to you when I am back. We apologies for the inconvenience, I appreciate your patience.

[nome]

Hello,

Thank you for your reply.

I have checked many times, and the "node name" and PIN_17 has the exact same name because SPI and UART in the Nios ii  processor are working perfectly.

However, whenever I add the PLL output connected to the DDR2 IP clock, critical warnings occur.

Thanks, Nome

[EBERLAZARE_I_Intel]

Hi,

Can you get me the full error list? I think there are some error related to the error you mentioned.

Anyway, I recommend that you could port over from this design to your device, it has the DDR and PPL connection in place:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/exm-accelerated-fir.html

[EBERLAZARE_I_Intel]

Hi,

Do you have any further update?

[nome]

Hello

Thanks for your Comments 

Warning (15899): PLL "nios_cpu:inst0_nios_cpu|lms_ctr:lms_ctr_inst0|lms_ctr_ddr2_1:ddr2_1|lms_ctr_ddr2_1_controller_phy:lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy:lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy:lms_ctr_ddr2_1_phy_alt_mem_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_clk_reset:clk|lms_ctr_ddr2_1_phy_alt_mem_phy_pll:half_rate.pll|altpll:altpll_component|altpll_mto3:auto_generated|pll1" has parameters clk2_multiply_by and clk2_divide_by specified but port CLK[2] is not connected

Warning (15899): PLL "nios_cpu:inst0_nios_cpu|lms_ctr:lms_ctr_inst0|lms_ctr_pll_0:pll_0|lms_ctr_pll_0_altpll_ecm2:sd1|pll7" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected

I am not understand why these  above warnings  occurs?

Thanks 

Nome

[EBERLAZARE_I_Intel]

Hi,

Can you use this design to see the connection and use it as template for your board? You may remove other IP that you're not using and update the top level after:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/exm-accelerated-fir.html

Maybe you can also share your design?

[EBERLAZARE_I_Intel]

Hi,

Can you check my previous post?

[EBERLAZARE_I_Intel]

Hi,

Try use this design to see the connection and use it as template for your board. You may remove other IP that you're not using and update the top level after:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/exm-accelerated-fir.html

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

[nome]

Hello
Thanks for your comments
I have custom board can't change any ddr2 inclock pins because its own old nios processor working excellent
we are still facing critical warnings from pll inclk

please help us
Thanks
nome