DDR2 high performance OCT assignments, clocking

[Altera_Forum]

Hello! 

 I'm currently trying to put two synchronized DDR2 I/F on top and bottom of my Stratix III (EP3SL70) FPGA. I started with one I/F and had a hard time to get it run. I found out, from the assignments of a former (working) one, that the followng assignments where missing:   set_location_assignment PIN_AG25 -to termination_blk0~_rup_pad set_location_assignment PIN_AH25 -to termination_blk0~_rdn_pad   Running the *_pin_assignments.tcl obviously didn't generate those assignments, so I added them by hand and it worked. However until now, I havent found anything in the doc (DDR2 H.P. user guide, AN462) about how to deal with this dynamic calibration OCT stuff. On my board, all 4 pairs are connected (AH25/AG25, AD7/AC7, A4/B4 and E22/F22). But currently, I have no clue how this has to be dealt with (what to be assigned etc.).    Has anyone found documentation (or any other link) on this? Would be glad for a pointer to it!   Another issue: I intend to feed a (50MHz) clock from a side input through a global clocknet to the top and bottom DDR2 PLL's. The synthesizer reacts with critical warnings and asks for direct feed-in at the PLL location (top and bottom). My feeling is, that skew is less, if I distribute it from one entry point on the FPGA through a global clock net compared to 2 or 3 FPGA entry points distributed on the board (either in a row giving skew or in a star giving unwanted echoes...). Finally, I need one synchronized 200 MHz System Clock (phy_clk), that I intend to get by forced merge of static clocks (as described in AN462). Anybody got experience with a similar environment?   Regards, Peter