FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

DDR2 termination

Altera_Forum
Honored Contributor II
799 Views

hi all, 

Today I study Altera develop board for DDR2 reference design. the develop kits is stratixIII_3sl150_dev. 

From this refer schematic, I found that for discrete DDR2 chip, there is 100 ohm resistor between clk_p/clk_N, but for DIMM DDR2, there is no resistor like this. 

From Altera DDR2 refer design named s3_host_ddr2_400mhz.qar, I found that there is serial 50ohm constraint to clk_p and clk_n. This refer design is for DIMM DDR2. So I want to confirm there should be no serial 50ohm for discrete DDR2 because there is external resistor for clk signal, right? 

 

Do you find any reference design for discrete DDR2? I want to study the constraint for DDR2 interface. 

 

Regards 

Tom
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
93 Views

Differential clock 100 ohms parallel termination at the RAM side is used for all DDR2 types, but with DIMM, it's provided on the module. 50 ohm source side series termination should be present for all types as well. I think, there is no effective difference between "discrete" RAM and unbuffered modules.

Altera_Forum
Honored Contributor II
93 Views

hi FvM, 

Thank you .
Reply