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DDR3_CONTROLLER problem

Altera_Forum
Honored Contributor II
917 Views

Hi, 

There is an error when I complie the DDR3 controller simulation design: 

 

Error (17044): Illegal connection found on I/O input buffer primitive DDR3_example_sim_e0:e0|DDR3_example_sim_e0_if0:if0|DDR3_example_sim_e0_if0_p0:p0|DDR3_example_sim_e0_if0_p0_acv_hard_memphy:umemphy|DDR3_example_sim_e0_if0_p0_acv_hard_io_pads:uio_pads|DDR3_example_sim_e0_if0_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|strobe_in. Source IO DDR3_example_sim_e0:e0|DDR3_example_sim_e0_if0:if0|DDR3_example_sim_e0_if0_p0:p0|DDR3_example_sim_e0_if0_p0_acv_hard_memphy:umemphy|DDR3_example_sim_e0_if0_p0_acv_hard_io_pads:uio_pads|DDR3_example_sim_e0_if0_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|obuf_os_0 also drives out to other destination than the buffer. 

 

The error points to the following code: 

 

if (DIFFERENTIAL_CAPTURE_STROBE == "true") 

begin 

cyclonev_io_ibuf 

# ( 

.differential_mode(DIFFERENTIAL_CAPTURE_STROBE), 

.bus_hold("false") 

) strobe_in (  

.i(capture_strobe_ibuf_i), 

.ibar(capture_strobe_ibuf_ibar), 

.o(dqsin), 

.dynamicterminationcontrol(1'b0) 

); 

end 

else 

begin 

cyclonev_io_ibuf 

# ( 

.bus_hold("false") 

) strobe_in (  

.i(capture_strobe_ibuf_i), 

.o(dqsin), 

.ibar(), 

.dynamicterminationcontrol(1'b0) 

); 

end 

 

 

Have anyone meet this error before?
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
133 Views

Are you sure the dynamic control should be ground? If you did not chane it, then ok 

 

Next thing, the error means that component there, is making an illegal conection, perhaps it is bidirectional and it is connected to something unidirectional outside. Perhaps it is connected to the wrong type of pin, perhaps it is connected to multiple pins outside on your top level (note that the second error says it "also drives out other destination than the buffer"). 

 

Here is the help saying what that means: 

http://quartushelp.altera.com/13.1/mergedprojects/msgs/msgs/escl_scl_illegal_wys_io_ibuf.htm 

 

Perhaps one of these gives you a hint, someone had this on a Stratix IV part: 

 

http://www.alteraforum.com/forum/showthread.php?t=5825
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