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DDR3 FPGA EMIF - Bank Interleaving for VIP Memory Bandwidth Efficiency

Altera_Forum
Honored Contributor II
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Hi 

 

 

I read in various VIP reference design documents that bank interleaving helps with memory bandwidth efficiency (for VIP deinterlacer and frame buffer). Can you someone explain how to setup this bank interleaving? 

 

 

In the Cyclone V FPGA DDR3 memory controller, should I use address mapping as CHIP-ROW-BANK-COL or CHIP-BANK-ROW-COL? Also how should I select the base addresses for the deinterlacer and frame buffer block for bank interleaving? 

 

 

For my system, I have two deinterlacer and two frame buffers. DDR3 physical i/f is 32bit wide with total of 1GB capacity. The Avalon-MM i/f from the deinterlacer or frame buffer to the memory controller is 128bit wide. 

 

 

Appreciate the help!
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