FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

DDR3 IP core clock

shandeep
Novice
408 Views

hi 

 Can i connect the pll_refclk input in the DDR3 ip core by  using a PLL ip core. Does the pll_refclk input in the DDR3 core has to be provided by means of an oscillator. 

0 Kudos
3 Replies
AdzimZM_Intel
Employee
392 Views

Hello shandeep,


You can connect it with the PLL IP but I think you need to close the timing issue due to that connection.

It's should be connected to the clock source pin.


You should refer to the EMIF User Guide in Chapter 6: DDR3 - Pin and Resource Planning.


Thanks,

Adzim


0 Kudos
shandeep
Novice
382 Views

hi AdzimZM 

 Thanks for your advice.

with regards 

shandeep 

0 Kudos
AdzimZM_Intel
Employee
375 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


0 Kudos
Reply