DDR3 IP with Uniphy PLL_AFI_CLK timing closure problems

[Altera_Forum]

Reposting this from General Discussion. 

 ===== Hello,  I'm experiencing some problems compiling a project that uses a DDR3 IP with UNIPHY on an ARRIA V FPGA. I'm getting critical warnings of not meeting timing related to PLL_AFI_CLK which points to the internal logic of the IP itself.  The IP is generated using MegaWizard. Anyone out there familiar with what i'm seeing?  I'm also currently trying one of Rysc reply post relating to Timing Optimization Advisor. Not much success at the moment.  Thanks, xslik =====

[Altera_Forum]

Hi xslik, 

 Did you find something, I got the same problem. I'am using the Quartus 12.1 to compile a design with DDR3 using the Hard memory IP :  pll_afi_clk warning in the setup time in the TimeQuest Timing Analyser reports.  Does anybody can help us ?   Thanks

[Altera_Forum]

By my thinking the Arria V timing models are still only preliminary, so I guess for the moment you'll just have to ignore those warnings.

[Altera_Forum]

Hello, 

I thought for general information, I'd do what Altera do not do, and fully document the DDR3 interface we made using Qsys, running 64 bits wide with 4 x Winbond W631GG6KB-15 or Micron MT41J64M16-15E DDR3 rams (64M x16).   In our board we used 145/250/145 um design rules for the clock diff pair, with a track length of 47mm, with a propagation velocity of 5.68ps/mm or 267ps. By way of comparison, the Altera Arria V starter kit has a track length of 63.5mm, with velocity of 5.95 ps/mm or 378ps.   We tested our board with Fclk = 300, 400 and 450 MHz (which is all we need). We are using an Arria 5AGXBA1D4F31C5N. We used the External Memory Interface Toolkit to do the margin reports. Timequest did not report any Timing problems. We used Quartus 13.0 SP1 (subscription edition)  I hope this helps.   Bart Cleverscope