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DDR3-IPcore clock frequency

Honored Contributor II

hello everyone. 


I have a little question about DDR3-IP core. 


my environment is ... 


QuartusII: version 13.0 

IP: DDR3-SDRAM controller with ALTMEMPHY v13.1 


I have set 100MHz for "PLL reference clock frequency" . 

and memory clock frequency is 300MHz 


and I input 100MHz to pll_ref_clk pin as I set above. 


then this IP-core does not work ( init_done is stacking LOW ). 


I had no idea about this and tried many things. 

then I found that when I gave 50MHz clock to pll_ref_clk, DDR3-SDRAM works well. 

the "PLL reference clock frequency" is still 100MHz. 


I don't understand what happens. 


can anybody tell what do I miss? or is that correct?
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