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Altera_Forum
Honored Contributor I
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DDR3 UniPHY controller on Stratix V initialization and calibration failed

Hi all, 

 

We are trying to implement a DDR3 UniPHY controller on Stratix V. Unfortunately when running the example design generated by the MegaWizard on board it always reports calibration failure (init_done is low, local_cal_fail is high, etc). We are pretty sure that we use correct timing parameters when generating the IP and acceptable memory clock frequency (actually we have tried 800M, 667M, 533M, 300M, etc). Also we are using the correct pin assignment for our own PCB. However, if we run the generated example design on the Stratix V devkit it works well. The only difference is the timing parameters and pin assignment. 

 

Does andbody have any idea about what might go wrong or how to debug it?  

 

Thanks in advance
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