Dear all, I feel SGDMA control is so ambiguous, several questions puzzle me:
1) What the IRQ number to use for communication between PC and FPGA using SGDMA? How to check which IRQ can be used?
If communication is between FPGA to external DDR, there is no need for IRQ?
2) What is the step by step procedure? The datasheet mostly gives the diagram, meaning of each bits, APIs. but what to do step by step and why?
3) What is the meaning and use of "translation register" with address of 0x1000-0x1004? in the PCIe wiki example
http://www.alterawiki.com/wiki/pci_express_in_qsys_example_designs // trying and check the address translation path through
OnRCSlaveWrite(hDev, 2, 0x1000, 0xFFFFFFFC); //0x1000 is the offset for translation register
// reading out the resulted mask of path through
UINT32 a2p_mask = OnRCSlaveRead(hDev, 2, 0x1000);//0x1000 is the offset for translation register
// program address translation table
// PCIe core limits the data length to be 1MByte, so it only needs 20bits of address.
OnRCSlaveWrite(hDev, 2, 0x1000, dma_buff.Page[0].pPhysicalAddr & a2p_mask); //setting lower address
OnRCSlaveWrite(hDev, 2, 0x1004, 0x0); // setting upper address limited at hardIP for now.
Thank you very much!
