DDR3 UniPHY master/slave

[EBoln]

To minimize the use of PLL, we decided to use PLL Sharing, but Fitter swears at the impossibility of placing the DLL. I did not find any examples on the Internet

[NurAida_A_Intel · Accepted solution]

Dear EBoln,

Thank you for joining this Intel Community. I am sorry for the delay in response as I were out of office due to medical leave.

I can see that your design contained Hard memory controller (HMC) which is fixed at Bank 7A and 4A for Cyclone V C7 device. Unfortunately, for HMC there is no sharing allowed for DLL due to its architecture. So, the fitter error seen is expected.

As shown in diagram below, you can see that the DLLs can access the two adjacent sides from its location in the device or in other word Bank 7 and Bank 6 for top DLL and Bank 5 and Bank 4 for bottom DLL . Since, the HMC is fixed at Bank 7A and Bank 4A, so there is no way to share the DLL.

You may refer to this CV handbook under section "DQS Phase-Shift Circuitry" for more details. -->

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v2.pdf

Hope this helps. Kindly let me know if you have any further question.

Thanks

Regards,

Aida

[EBoln]

Thank you! Close pls

[NurAida_A_Intel]

You are more than welcome and thank you for your confirmation. Hope I can serve you again in future.

I am now setting this case to closure. 

Have a nice day ! 😊

Regards,

Aida