FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5953 Discussions

DDR3 Uniphy- Hard memory controller with MPFE.

Altera_Forum
Honored Contributor II
907 Views

Hello, 

I'm using Arria V GT dev kit, DDR3 SDRAM Uniphy IP, Hard memory controller with Multi port front end (MPFE). I'm using 2 ports, First port for Write_only and second port for read_only and trying to write some set of data to DDR memory with Burst lenth =8 and read back the same with BL=8. But i'm unable to read my data back, because data_valid signal never goes HIGH. 

 

I'm using Micron device= MT41J128M16HA-125D. 32MX16X8, 2GB, DDR Memory. 

-------------------------------------------------------------------------------------------------------------------------------------------------------  

TEST- 1 

write side => BL = 8, Data_write = 32 bit, write_request = 8 clk cycles, Byte_En = Fh , Burst_begin = 1 for one cycle at start of the burst and address ="0000000". 

 

Read side => BL=8, Data_read =32 bit, read_request = 8 clk cycles, Byr_En =Fh, Burst_begin =1 for one cycle at start of the address and address ="000000". 

 

Result => with read_request = 8 times(8 clk cycles) and BL= 8. I'm getting 64 times (64 clk cycles) of data valid. Im able to read my data along with some junk data. 

-------------------------------------------------------------------------------------------------------------------------------------------------------------- 

 

TEST- 2 

 

Write side => same as TEST-1 

read side => same as Test-1, but only 4 times read_request with BL= 8, then  

result => with read_request = 4 times(4 clk cycles) and BL= 8. I'm getting 32 times (32 clk cycles) of data valid. Im able to read my data along with some junk data. 

----------------------------------------------------------------------------------------------------------------------------------------------------------------- 

TEST- 3 

 

Write side => same as TEST-1 

read side => same as Test-1, but only 2 times read_request with BL= 8, then  

result => with read_request = 2 times(2 clk cycles) and BL= 8. I'm getting 16 times (16 clk cycles) of data valid. Im able to read my data along with some junk data. 

--------------------------------------------------------------------------------------------------------------------------------------------------------------- 

TEST- 4 

 

Write side => same as TEST-1 

read side => same as Test-1, but only 1 time read_request with BL= 8, then  

result => with read_request = 1 time(1 clk cycle) and BL= 8.  

 

Data_valid signal never trigger. Data_read = "0000000000". so No data read . 

---------------------------------------------------------------------------------------------------------------------------------------------------------- 

 

what could be the reason..?? 

If suppose I'm writing 32 bit of data, 8 times with BL=8, then while reading back How many times should i enable the read_request signal with BL=8...??
0 Kudos
0 Replies
Reply