Hi,I want to use a third party verification tool (ModelSim), that supports only Verilog (and SV). Trouble is, my design includes several FIR filters, which have a "A VHDL wrapper file for the Avalon-ST interface" as the FIR compiler and FIR compiler II user guide states. This is the only VHDL file, in a completely Verilog design. I've checked, and seen no way to configure the FIR compiler to generate the wrapper in Verilog instead. Although the translation from VHDL to Verilog will not be very intricate, I still rather circumvent this solution, Because it is manual and therefore not scalable, and prone to bugs. Do you have any idea how to mitigate this? Thanks, David
Modelsim supports mixed language if you have an expensive enough licence.Otherwise, you need to re-write the VHDL to Verilog. Otherwise write your own, Parameterisable avalon ST wrapper. Its not a very complicated interface (with a ReadyLatency setting of 0 - it can connect directly to a lookahead FIFO).
With the free version of Modelsim (10.3d) which comes with Quartus 15.0, you can do mixed mode simulation, including of the FIR filters. In fact it's the only reason I upgraded from 14.0 to 15.0.