I am tring to add DDR3 controller IP to my current project, but after implementation Quartus 18.1 show timing violations on paths from afi_clk to pll_hr_clk (200 MHz -> 400 MHz). Clock frequency of DDR3 memory is 800 MHz. FPGA is Stratix V. FPGA resources used about 66%.
When exploring timing violation in the TimeQuest I see that there is big skew (~ 800 ps) between this two clocks although they are different outputs of the same pll.
I must to note that after run the p0_pin_assignment.tcl script in the qsf-file written assignment for pll_hr_clk put it on DUAL-REGIONAL CLOCK network and afi_clk to GLOBAL CLOCK.
In the GUI of the DDR controllet IP there is no settings for shifting these two clocks one relative another.
When I try to set phase adjustment directly in the generated sources for pll not help (it is possible that I set not applicable settings)
Also I didn't find the fitter and QSF settings which can help.
If someone can help me with this I will be very appreciate.
Thank you in advance