FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5749 Discussions

DDR4 calibration failures on Terasic PCB

SSilu
Beginner
285 Views

I encounter intermittent calibration failures on Terasic DE5A-NET when using Kingston KVR24S17S8_8 memory. Calibration always passes on default memory modules shipped with Terasic PCB MTA4ATF51264HZ-2G3(4GB). I assume both modules are compatible PC4-2400 and should work on the same IP parameters. Quartus 20.1. Please find attached:

  • Calibration pass/fail reports for Kingston at ref freq = 267M
  • Plot of failures ratio in function of frequency (ddr A - Kingston; ddr B - Micron)
  • Emif IP used
  • Micron data sheet

Moreover I observed strange behaviour regarding Bank Group pin width. In default memory IP from Terasic BG width = 1 - as in Micron memory. Kingston has BG[2]. I expected to simply run Kingston on default Terasic IP with half of memory (512M instead of 1G). However what I got was consistent calibration failures. When I extended BG to 2 calibration sometimes passes as on attached plot.

0 Kudos
3 Replies
ybin
Employee
272 Views

1. For the BG width, you should follow vendor's datasheet. As it's BG of Micron's is 1, the IP setting should be the same as it.

2. Normally, the clock should be 266.67Mhz, not 267Mhz, you can correct it. 

3. Different vendor's datasheet should be different. For the memory timing parameter in IP MEM timing tab & memory tab,  you should follow Micron's and modify it accordingly. I can't find any MEM timing in attached datasheet, you can contact with Micron and get the related MEM timing parameter. 

4. For board tab parameter, normally you need do SI simulation with vendor's simulation model to determine the SI/corsstal value. Pls refer to below link for more detail.

https://community.intel.com/t5/FPGA-Wiki/Board-Skew-Parameter-Tool-Guide/ta-p/735276

5. After input the correct parameter, you can compile the design, and make sure there is no timing violation warning.

ybin
Employee
264 Views

The basic device for sodimm is  MT40A512M16,  but there are 3 part number, G6/G3/G1 according to sodimm datasheet. You can get the correct datasheet(G6,G3, or G1) and check the parameter. If you still have concern about MEM timing tab parameter after you get the correct datasheet, please update it in attachment and let me know.

ybin
Employee
244 Views
We do not receive any response from you to the previous question/reply/answer that I have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.
Reply