Hello,I'm using the Qsys SDRAM controller for the 2 SDRAM chips(IS42S16320D) on the DE2-115 boards (Cyclone IVE). I'm giving the SDRAM chips a 133MHz clock which leads the 133MHz controller clock by 3 ns (using a PLL). The system clock is 50 MHz. SDRAM configuration: CAS Latency -> 2 init refresh cycles -> 8 refresh command every 8 microseconds 100 microsecond delay after power up refresh command duration -> 29 ns precharge command duration -> 15 ns ACTIVE to READ or WRITE delay -> 15 ns Access time -> 5.4 ns Write recovery time -> 20 ns Bus width -> 32 bits Rows -> 13 Cols -> 10 Chip select -> 1 Banks -> 4 I attempt to write to two addresses sequentially, 0xDEAD_BEEF to address 0xA5A5A5 in the first write and 0xFEED_BABE to address 0xA5A5A6 in the second cycle. About one hundred cycles later, I attempt to read from the same addresses and get 0xF00FF00F. Can anyone make recommendations as to what I might be doing incorrectly? I've included a SignalTap waveform of the specific signals I am setting (write enable/read enable/etc) and receiving on the lines. To be clear, I am not interfacing with the NIOSII core. I am seeking a fabric-only solution to this. SignalTap screencaps: imgur dot com/e7v8L,gJIwR (sorry for circumventing the 5 post before images rule) az_rd_n -> Controller read enable az_wr_n -> Controller write enable zs_dq -> Data lines from controller to SDRAM az_data -> Data from controller to FPGA fabric (data read from SDRAM) za_data -> Data to controller from FPGA fabric (data written to SDRAM) az_addr -> Address being written to/read from za_waitreqest -> asserted when the controller cannot take a read/write command za_valid -> asserted when the data read from SDRAM is valid Thanks! Ryan
If anyone has gotten the SDRAM controller to successfully write and read anything to the DE2 SDRAM chips, could you describe your process? I've been working on this for a while without any luck.