Honored Contributor I
01-26-2013 05:10 PM
Hello!I need to construct integrator and differentiator blocks in advanced blockset, so I need some delay to store previous data. I don't know how to do this, because there is different latency of blocks and there are errors about combinational loops. I think I could use valid signal, but don't know exactly how. And another problem is that sample time and clock frequency are different in my design. Help needed. Thank you.