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Slow Avalon I2C Master FPGA IP Response

n_nuti
Employee
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Hello,

 

We're using the Avalon I2C (Master) Intel FPGA IP in QSYS with the NIOS II processor, and we're using it to communicate with an HDMI sink.

 

For TX we use "alt_avalon_i2c_master_tx" function and for RX we use "alt_avalon_i2c_master_tx_rx()".

 

The NIOS control and QSYS settings can be seen in the attached images.

 

When we try to use the I2C IP to complete two reads (tx then rx) in a row, we're seeing over 150 ms of delay between the two reads (tx then rx). I've included a scope capture that shows this delay. Why is this delay happening? We're running HDMI link training and need our transmissions to happen at a much more rapid pace.

 

Thank you,

Nick

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KellyJialin_Goh
Employee
446 Views

Hi,

Kindly have a look at the I2C core API and the limitations as the API may wait for certain controller states before completing which resulted in the delay: https://www.intel.com/content/www/us/en/docs/programmable/683130/21-3/fpga-i2c-host-core-api.html


Thank you.

 

Regards,

Kelly



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KellyJialin_Goh
Employee
389 Views

Hi,


Any updates from you end whether the feedback provided is useful?


 Thank you.


Regards,

Kelly


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KellyJialin_Goh
Employee
366 Views

Hi,

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


Thank you.

Regards.

Kelly Jialin, GOH

 



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