Hi , im just perform RTL simulations with the ModelSim software. I add a TestBench block to my DSP builder model. Then I get the following error:
# ** Error: (vsim-3817) Formal port "clk" declared in the entity is not in the component. # Time: 0 ps Iteration: 0 Region: /tb_dpt2/dut File: ../DSPBuilder_dpt2_import/dpt2.vho # ** Error: (vsim-3817) Formal port "reset" declared in the entity is not in the component. # Time: 0 ps Iteration: 0 Region: /tb_dpt2/dut File: ../DSPBuilder_dpt2_import/dpt2.vho # ** Error: (vsim-3817) Formal port "data_in1" declared in the entity is not in the component. # Time: 0 ps Iteration: 0 Region: /tb_dpt2/dut File: ../DSPBuilder_dpt2_import/dpt2.vho # ** Error: (vsim-3817) Formal port "data_in2" declared in the entity is not in the component. # Time: 0 ps Iteration: 0 Region: /tb_dpt2/dut File: ../DSPBuilder_dpt2_import/dpt2.vho # ** Error: (vsim-3817) Formal port "data_in3" declared in the entity is not in the component. # Time: 0 ps Iteration: 0 Region: /tb_dpt2/dut File: ../DSPBuilder_dpt2_import/dpt2.vho # ** Error: (vsim-3817) Formal port "data_in4" declared in the entity is not in the component. # Time: 0 ps Iteration: 0 Region: /tb_dpt2/dut File: ../DSPBuilder_dpt2_import/dpt2.vho # ** Error: (vsim-3817) Formal port "data_in5" declared in the entity is not in the component. # Time: 0 ps Iteration: 0 Region: /tb_dpt2/dut File: ../DSPBuilder_dpt2_import/dpt2.vho # ** Error: (vsim-3817) Formal port "data_in6" declared in the entity is not in the component. # Time: 0 ps Iteration: 0 Region: /tb_dpt2/dut File: ../DSPBuilder_dpt2_import/dpt2.vho # ** Error: (vsim-3817) Formal port "data_in7" declared in the entity is not in the component. # Time: 0 ps Iteration: 0 Region: /tb_dpt2/dut File: ../DSPBuilder_dpt2_import/dpt2.vho # ** Error: (vsim-3817) Formal port "data_in8" declared in the entity is not in the component. # Time: 0 ps Iteration: 0 Region: /tb_dpt2/dut File: ../DSPBuilder_dpt2_import/dpt2.vho # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'input3' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'output4' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'input7' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'aclr' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'input8' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'clock' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'input4' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'output5' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'output1' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'output6' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'input5' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'input' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'output' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'dpt2_subsystem_output8' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'input2' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'output2' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'input6' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'output7' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'input1' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'output3' is not on the entity.) # Region: /tb_dpt2/dut # ** Fatal: Bad library format, library not compiled with ALTERA compiler. # # Time: 0 ps Iteration: 0 Instance: /tb_dpt2/clock File: UNKNOWN Line: 293 # FATAL ERROR while loading design # Error loading design # Unrecognized dataset prefix: sim can someone help me with this? thanks !!!連結已複製
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It might help if you gave a little more information. Does your design compile in Quartus? Does it simulate correctly in Simulink?
Perhaps post a screenshot of your design if not the design (cut down as much as possible to demonstrate the failure) itself.--- Quote Start --- It might help if you gave a little more information. Does your design compile in Quartus? Does it simulate correctly in Simulink? Perhaps post a screenshot of your design if not the design (cut down as much as possible to demonstrate the failure) itself. --- Quote End --- thanks for the reply! yes it compiled smoothly in quartus and run perfectly in simulink. and all the port name mention in the error are from the attached vhdl file.
Is the name of your original VHDL file and the model the same?
It kind of looks like it's loading your top-level VHDL as the HDL Import or vice versa. If so try to make sure that the names do not clash.--- Quote Start --- Is the name of your original VHDL file and the model the same? It kind of looks like it's loading your top-level VHDL as the HDL Import or vice versa. If so try to make sure that the names do not clash. --- Quote End --- hmmm..im pretty sure there is no clash between the name of the file and the model...
I should have clarified it's the name of the entity in the file not the file itself that will clash.
In your original log you have tb_dpt2, which seems to indicate your original model was called dpt2. It also references DSPBuilder_dpt2_import/dpt2.vho, which would indicate you imported a file called dpt2.vhd via HDL Import. Also you might have some stale files around. Try deleting the DSPBuilder_dpt2_import and tb_dpt2 directories and regenerate.--- Quote Start --- I should have clarified it's the name of the entity in the file not the file itself that will clash. In your original log you have tb_dpt2, which seems to indicate your original model was called dpt2. It also references DSPBuilder_dpt2_import/dpt2.vho, which would indicate you imported a file called dpt2.vhd via HDL Import. Also you might have some stale files around. Try deleting the DSPBuilder_dpt2_import and tb_dpt2 directories and regenerate. --- Quote End --- thank you very much! i got this problem solved!! in the model, i set the inputs through the matlab function blockset with function defined as: double(rgb2gray(imread('pic.tif'))) but why cant this value been shown in the modelsim?
and i have the following error message when i Compare Simulink Result with Modelsim:
Error: Error opening HDL output file dpt2_Output.capture.msim :: Missing data type 'null' in file dpt2_Output.capture.msim Error: Mismatch between ModelSim and Simulink outputs. Please refer to the DSPBuilder trouble-shooting guide for more information.Btw, have you tried compiling your DSP Builder design in Signal Compiler yet? Judging from the error statement, there is a chance that your IP cache folder got corrupted (it happens from time to time, especially when you migrate from one version of DSP Builder to another)...
I would suggest the following: 1. Delete the existing IP cache folder(s) in your computer... Go to C:\Documents and Settings\<User Name>\ --> Inside that folder, you should see a .altera.quartus folder 2. Delete that folder and restart your DSP Builder... see if you still see the same error... Best of luck.