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DSP Builder to Modelsim II

Altera_Forum
Honored Contributor II
‎02-13-2009 04:52 PM
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Hi I have the following a HDL import of the following vhdl file to dsp builder simulink. 

 

Hoewever I didn obtain correct output from the modelsim simulation or I would rather say that most of the outputs display '-' or 'X' and I have tons of following error: 

 

There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 

 

I followed several suggestion from the net but still to no success. Can anyone help me to take a look at my attached vhdl file and advise me on how to change my coding??
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Altera_Forum
Honored Contributor II
‎02-14-2009 09:23 AM
224 Views

Hi all, I realized where is the mistake. I didn not reset/declare the signal properly that caused the value undefined appear in the simulations

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