FIR Filter with Coefficient Reload

[Altera_Forum]

Hello, 

 I'm trying to design an FIR-Filter for a StratixII Board. The design should have the Coefficient Reload option so that I can load new coefficients with an external PC to the Filter at the end.  My Problem is how to start! Should I use an IP Megacore DSP Function (FIR Filter with Coefficient Reload) or should I try to design it my way with the DSP Builder Kit? Or any other way i do not know yet?  I would be thankfull for any help!

[Altera_Forum]

You can use the Atera fircompiler Megacore. There is an option to reload the coefficients dynamically. 

See the document  http://www.altera.com/literature/ug/fircompiler_ug.pdf  at page 44. Hope this helps.

[Altera_Forum]

If you implement your own design using an altsyncram megafunction, it's possible to modify its contents by means the "in system memory content editor". You must allow this feature in the megawizard plugin manager

[Altera_Forum]

I understand what you mean. I don't change the coefficients in the filter directly. The filter uses the coefficients in this RAM which I can change. 

 But there is no "in system memory content editor" in the Mega Wizard Plugin Manager. Is it only available in Quartus 8? I'm using v6

[Altera_Forum]

You could also use the DSP Builder Advanced blockset: http://www.altera.com/technology/dsp/advanced-blockset/dsp-advanced-blockset.html 

 This has it's own FIR blocks, and some simple demo designs to get you started. If you set the coefficients to be writeable, a memory-mapped interface is created, so you can connect this up in SOPC Builder.

[Altera_Forum]

I have been able to get this to work with just the plain Megacore version of a FIR filter (I had posted in a different thread....see below). The trick there is that you need to modify your coeff's using an executable provided by Altera (coef_seq.exe), in order to get it to work. If you have plenty of space, it's no big deal to store them (my 11 18-bit coefficients turned into something like 64 24-bit values) and then push them in via the coef_ld ports on the FIR filter. I peeled apart what was actually being done to the values, and it was dividing them up into a massive sum-of-products tree. I was able to mimic this in logic, because I really only had space in my device for 11 of the 18-bit values. 

 I was able to get the reloadable filter design working on the bench, and was able to manually input coefficients (using Nios) into my custom logic, and it passed the values into the FIR w/ the coef_seq formatting. I was able to create LPF and HPFs w/out reloading the FPGA. Worked out pretty well, although not horribly intuitive. The link to my other post is here:  http://www.alteraforum.com/forum/showthread.php?t=838&highlight=fir+reload  Anyways, I was wondering if anyone's tried the register-access FIR reload function in the DSP builder advanced blockset. I'm a bit intrigued by it, since it seems like it would work pretty well. From what I can tell, you establish a base address for each module in the design, and then the individual coefficients would be BASE_A+0, BASE_A+1 ... BASE_A+(NUM_COEFF-1), as long as you make the data width wider than the widest coefficient. Can anyone confirm if that assumption is true, before I dive into it?  Jeff

[Altera_Forum]

I briefly looked into it and it sounds like your assumption is right (that's how it should be according to the UG anyways)...