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Altera_Forum
Honored Contributor I
938 Views

Data width in the Avalon-MM Write FIFO in DSP Builder

Hi, 

 

In my design in DSP Builder I am using the block Avalon-MM Write FIFO because I want to include it in a SOCP system. In the data width of the block I write 1 and in the FIFO Depth 16. 

The simulation in Simulink run properly but when I build the nios II system in SOPC Builder I obtain an error with the data width in Avalon Bus 

ERROR: 

slave data width (1) for slave my_Scrambler/Avalon_MM_Write_Slave unexpected 

Error: Generator program  

for module 'cpu' did NOT run successfully. 

 

The data width of Avalon Bus is 32 and the data width of my DSP Builder system is 1. Do I have to change the data width in the block Avalon-MM Write FIFO and put 32? Or am I doing something wrong? 

 

Thanks.
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1 Reply
Altera_Forum
Honored Contributor I
29 Views

the width of your data path is 1 bit? Avalon-MM is byte adressable, not bit addressable...

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