FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Datasheet/Documentation

ggxnd
Beginner
671 Views

I couldn't find datasheet of PHYLITE for parallel interface ip specific to Agilex 5 E-series devices whereas it is available for Agilex 7 devices. Will the pin planning constraint rule are similar to all Agilex devices or is there datasheet available specific to Agilex 5 E-series? Kindly let me know the details.

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sstrell
Honored Contributor III
637 Views

Is PHYLITE even supported in Agilex 5?

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JingyangTeh
Employee
619 Views

HI ggxnd


Which company are you working with?

There is an on going EAP (Early Access Program) for the Agilex5.

If your are registered or interested you could pass the interest to your distributor or FAE on this.


Regards

Jingyang, Teh


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JingyangTeh
Employee
558 Views

HI ggxnd


Any update on this case?


Regards

Jingyang, Teh


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JingyangTeh
Employee
534 Views

Hi


Since there are no feedback for this thread, I shall set this thread to close pending. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 4 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.


Regards

Jingyang, Teh


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