Debugging F-Tile Transceiver in TSE IP Core Using Transceiver Toolkit

[fa_fpga_enthusiast]

Hello,

Based on the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide, utilizing the Transceiver Toolkit for debugging an F-Tile transceiver—specifically to connect the Eye Viewer and run the BER Test—requires modifying the design to enable F-Tile transceiver debugging. According to the documentation, this involves enabling the Datapath and PMA Avalon Interface, Direct PHY Soft CSR, and Debug Endpoint options under the Avalon® Memory-Mapped Interface tab:

https://www.intel.com/content/www/us/en/docs/programmable/683872/22-4-4-3-0/modifying-the-design-to-enable-f-tile.html

However, when using the Triple-Speed Ethernet (TSE) IP core and selecting the FGT transceiver as the PCS, the PCS/Transceiver Options tab under the F-Tile FGT Transceiver Options section provides only the following two options:

• Enable Datapath Avalon Interface
• Enable PMA Avalon Interface

There are no additional options to enable the required debug ports for connecting the Transceiver Toolkit to the transceiver instantiated within the TSE IP core.

My question is: How can we connect the Transceiver Toolkit to the transceiver instantiated in the TSE IP core for debugging purposes?

I would appreciate any guidance or recommendations on enabling the necessary debug interfaces in this setup.

Best regards.

[paveetirrasrie_Intel]

Hello,

Good day to you.

It appears that Triple Speed Ethernet does not support the Debug Endpoint for TTK by default. But we would take this as improvement suggestion and will work on this in future.

Regards,

Pavee

[paveetirrasrie_Intel]

Hello,

We didn't hear from you since last update. If you have a new question, feel free to open a new thread to get the support from Altera experts. 

Otherwise, the community users will continue to help you on this thread. 

Thank you.