Debugging PCIe DMA transfer example design

[Sijith]

Hi,

I would like to have your continued support on this thread.  Unfortunately this ticket got closed https://community.intel.com/t5/FPGA-Intellectual-Property/A-design-based-on-the-PCIe-DMA-transfer-example-design-for-Arria/m-p/1579247#M28763

Thank you.

[ventt]

Hi @Sijith,

Could you please run the DMA read test to verify that the host can read the correct data written to the FIFO?

Also, please check my previous reply here. Usually, FIFO is used to buffer data streams and manage differences in data processing rates.

https://community.intel.com/t5/FPGA-Intellectual-Property/A-design-based-on-the-PCIe-DMA-transfer-example-design-for-Arria/m-p/1564164/highlight/true#M28507

Thanks.

Best Regards,

VenTingT

[Sijith]

Hi VenTing,

I ran the DMA read test and could not verify that we could read data that is being written to FIFO. Just a question, as the Signal Tap does not show the data flow to FIFO when it connects to the DMA design (as I mentioned in the last message) should be expect the DMA read to work?

I and currently I am trying to follow https://community.intel.com/t5/FPGA-Intellectual-Property/A-design-based-on-the-PCIe-DMA-transfer-example-design-for-Arria/m-p/1564164/highlight/true#M28507 and will update you.

Thank you

Regards

SE

[ventt]

Hi @Sijith,

Please note that in the design example, the DMA read/write operations are initiated from the host side to the FPGA side. To initiate the DMA read/write operations from the FPGA side to the host, users will need to modify the driver. Without the proper modification, the DMA operations may not be successful. Have you made the necessary changes to the driver to suit your current application?

May I know if you need more time to provide the update? 

It is advisable to keep the forum thread active, otherwise, I'll need to transition to community support. You may open a new post if you have further questions.

Thanks.

Best Regards,

VenTingT

[Sijith]

Hi VenTing,

The all change I made is in the "API.cc". file, instead of creating random number and sending that to DDR4, I retained only reading part of the code (I mean write DMA is disabled and only have read DMA), I am just curious that is this the thing I am suppose to do? If not what are the potential changes that we should make?  

Also, I would like to cross-check that during the Signal Tap capturing of the modified design, whether the Read DMA API is not suppose to run from host computer? (I mean to generate the trigger Avalon-MM read from the design (I mean from the unmodified part of the design) to the FiFO: I suspect the absence of this  signal to  FIFO cause no data from data generator (while running Signal Tap). Do you have any suggestion how to create those signals? Pls let me know if my question is not clear.

I really would like to have little bit more time to provide updates on https://community.intel.com/t5/FPGA-Intellectual-Property/A-design-based-on-the-PCIe-DMA-transfer-example-design-for-Arria/m-p/1564164/highlight/true#M28507. Thanks for the understanding

Regards

SE

[ventt]

Hi @Sijith,

I have reviewed the forum threads previously. Regarding the 'API.cc' file, are you referring to 'Demonstrations/PCIe_SW_KIT/Windows/PCIe_DDR4/PCIE_DDR4.cpp'? If so, you will need to modify the driver to suit the modifications you've made to the design example. As per my understanding, the PCIE_DDR4 application provided by Terasic is specifically designed for the PCIe Reference Design - DDR4. 

From the DE5a_Net_User_Manual.pdf:

In Chapter 7.3, the PCIe library module TERASIC_PCIE_AVMM.dll provides DMA and direct I/O access for user application program to communicate with FPGA. Users can develop their applications based on this DLL. 

In Chapter 7.4, below shows the exported API in the TERASIC_PCIE_AVMM.dll.

Perhaps you can start from here to modify the driver for your design application. Please note that driver support falls outside my area of expertise.

If you want to perform DMA read operation from host side, then it needs to run from the host. On the other hand, if you want to perform DMA write operation from the FPGA side, then you would need to modify the driver to initiate the DMA from the FPGA side.

Noted, and take the time you need. I look forward to your updates.

Thanks.

Best Regards,

VenTingT

[ventt]

Hi @Sijith,

Do you have any updates from the previous reply?

Thanks.

Best Regards,

VenTingT

[Sijith]

Hi VenTing,

Actually I am working on the DDR4 example design and anticipate a couple more days to finish. Would like to update you on this.

About your previous reply,

1) Yes I was referring to 'Demonstrations/PCIe_SW_KIT/Windows/PCIe_DDR4/PCIE_DDR4.cpp. Will just compiling this code will update the driver or I have to do something more. May I know which is the best place to ask question regarding the Driver modifications (Do you have experts providing support on the API drivers too?) for this example design?

2) In Chapter 7.3, the PCIe library module TERASIC_PCIE_AVMM.dll provides DMA and direct I/O access for user application program to communicate with FPGA. Users can develop their applications based on this DLL. 

I thought by disabling the writing part of API (PCIE_DmaWrite) in the `PCIE_DDR4.cpp.` file will do the work as it qualifies the description under `Chapter 7.3`. But not sure how to to modify the driver to initiate the DMA from the FPGA side. Any suggestion will be highly appreciated.

Thank you very much

Regards

SE

[ventt]

Hi @Sijith,

Thanks for the update.

From my understanding, if you're following the entire design provided (In Chapter 7.6 PCIe Reference Design - DDR4) with no modification, you can directly install the PCIe Driver and follow the steps to execute the application program, PCIE_DDR4.exe, provided by Terasic. This will allow you to perform 4 GB data DMA for both SODIMM as demonstrated in DE5a_Net_User_Manual.pdf, which you have previously tested.  

However, in your case, you have modified the design to suit your own application, which means you no longer wish to perform 4 GB data DMA for both SODIMM, I do not think merely making changes in ../PCIE_DDR4.cpp would be sufficient. In Chapter 7.4, subsection 'Create a Software Application', the necessary procedures to follow in order to create a desired application are outlined. I'm not certain if the TERASIC_PCIE_AVMM.dll consists of the API you need for your desired application. If it does not, you will likely need to modify the driver and create a new application. Please consult with the Terasic software application or driver expert on this matter.

Thanks.

Best Regards,

VenTingT

[ventt]

Hi @Sijith,

Any updates? Do you have further inquiries on this forum thread?

Thanks.

Best Regards,

VenTingT

[Sijith]

Hi VenTing,

I have wrote to Terasic to enquire about the Driver and waiting for their reply. Sorry for bit delay as I was stuck with an emergency task. Now I restarted working on I am working on the DDR4 example design. I would like to have a couple more days  to update. Thank you for the understanding.

Regards

Sijith E

[ventt]

Hi @Sijith,

Thank you for your update. I appreciate it very much.

I understand your situation. However, since you are currently awaiting a response from Terasic, I suggest closing this ticket as my support is no longer needed. Additionally, this thread has become quite lengthy, with multiple issues having been discussed back and forth.

Please feel free to open a new post with specific issues/questions if you still need further assistance. Someone will be right with you.

Thank you for your understanding.

Best Regards,

VenTingT