Debugging PCIe DMA transfer example design

[Sijith]

Hi,

I would like to have your continued support on this thread.  Unfortunately this ticket got closed https://community.intel.com/t5/FPGA-Intellectual-Property/A-design-based-on-the-PCIe-DMA-transfer-example-design-for-Arria/m-p/1579247#M28763

Thank you.

[ventt]

Hi @Sijith,

Could you please run the DMA read test to verify that the host can read the correct data written to the FIFO?

Also, please check my previous reply here. Usually, FIFO is used to buffer data streams and manage differences in data processing rates.

https://community.intel.com/t5/FPGA-Intellectual-Property/A-design-based-on-the-PCIe-DMA-transfer-example-design-for-Arria/m-p/1564164/highlight/true#M28507

Thanks.

Best Regards,

VenTingT

[Sijith]

Hi VenTing,

I ran the DMA read test and could not verify that we could read data that is being written to FIFO. Just a question, as the Signal Tap does not show the data flow to FIFO when it connects to the DMA design (as I mentioned in the last message) should be expect the DMA read to work?

I and currently I am trying to follow https://community.intel.com/t5/FPGA-Intellectual-Property/A-design-based-on-the-PCIe-DMA-transfer-example-design-for-Arria/m-p/1564164/highlight/true#M28507 and will update you.

Thank you

Regards

SE

[ventt]

Hi @Sijith,

Please note that in the design example, the DMA read/write operations are initiated from the host side to the FPGA side. To initiate the DMA read/write operations from the FPGA side to the host, users will need to modify the driver. Without the proper modification, the DMA operations may not be successful. Have you made the necessary changes to the driver to suit your current application?

May I know if you need more time to provide the update? 

It is advisable to keep the forum thread active, otherwise, I'll need to transition to community support. You may open a new post if you have further questions.

Thanks.

Best Regards,

VenTingT

[Sijith]

Hi VenTing,

The all change I made is in the "API.cc". file, instead of creating random number and sending that to DDR4, I retained only reading part of the code (I mean write DMA is disabled and only have read DMA), I am just curious that is this the thing I am suppose to do? If not what are the potential changes that we should make?  

Also, I would like to cross-check that during the Signal Tap capturing of the modified design, whether the Read DMA API is not suppose to run from host computer? (I mean to generate the trigger Avalon-MM read from the design (I mean from the unmodified part of the design) to the FiFO: I suspect the absence of this  signal to  FIFO cause no data from data generator (while running Signal Tap). Do you have any suggestion how to create those signals? Pls let me know if my question is not clear.

I really would like to have little bit more time to provide updates on https://community.intel.com/t5/FPGA-Intellectual-Property/A-design-based-on-the-PCIe-DMA-transfer-example-design-for-Arria/m-p/1564164/highlight/true#M28507. Thanks for the understanding

Regards

SE