FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Delay for video IPs

Honored Contributor II

I've seen that there's an ip to delay (to a max of 16 clock cycles) signals from avalon-ST. Unfortunatly, it does not support backpressure, so I suppose I can't use that to delay signal from streaming-video packet. 

I tryed to write a custom blok to delay my signals, but it does not seem to wok. Well, sop, eop etc seems to work properly, but i see something like a vertical square pulse in the middle of the screen. 


I only suppose that data_valid is not regular or has the same clock speed so it is not correcty stored in memory.  

I'd like to know HOW can I properly add a delay to my system 

Any hint would be appreciated.  


If someone could find it useful, the code I wrote is 



--- Quote Start ---  


module shift_reg_ram_12# (parameter LENGTH=11) 

input clk, 

input reset, 

input we, 


input dout_ready, 

input [15:0] din_data, 

input din_valid,  

input din_sop, 

input din_eop, 




output din_ready , 

output reg [15:0] dout_data, 

output reg dout_valid, 

output reg dout_sop, 

output reg dout_eop 




reg [19:0] mem [15:0]; 

reg [4:0] addr; 


always@(posedge clk) begin 

if (we) mem[addr] <= {din_data,din_valid,din_sop,din_eop}; 

{dout_data,dout_valid,dout_sop,dout_eop}<= mem [addr]; 



always @ (posedge clk or posedge reset) 


if (reset) 

addr <= 0; 

else if (we) begin 

if (addr<LENGTH) 

addr <= addr + 1; 


addr <=0;  



assign din_ready=we; 



--- Quote End ---  



Best regards 

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